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Searched refs:r1 (Results 1 – 25 of 118) sorted by relevance

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/u-boot/board/freescale/mx6sllevk/
A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
21 ldr r1, =0x00003030
[all …]
/u-boot/board/freescale/mx6ullevk/
A Dplugin.S11 ldr r1, =0x000C0000
12 str r1, [r0, #0x4B4]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x4AC]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x27C]
17 ldr r1, =0x00000030
18 str r1, [r0, #0x250]
21 ldr r1, =0x000C0030
24 ldr r1, =0x00000000
[all …]
/u-boot/board/freescale/mx7ulp_evk/
A Dplugin.S70 ldr r1, =0x00040000
72 ldr r1, =0x0
73 str r1, [r0, #0xf8]
74 ldr r1, =0x00000180
75 str r1, [r0, #0xd8]
76 ldr r1, =0x00000180
78 ldr r1, =0x00000180
80 ldr r1, =0x00010000
82 ldr r1, =0x0000018C
83 str r1, [r0, #0x80]
[all …]
/u-boot/board/samsung/goni/
A Dlowlevel_init.S47 and r1, r1, #0x000D0000
61 bic r1, r1, #(1 << 1)
88 bic r1, r1, #0x1
93 bic r1, r1, #0x1
98 bic r1, r1, #0x1
103 bic r1, r1, #0x1
108 bic r1, r1, #0x1
113 bic r1, r1, #0x1
156 orr r1, r1, r2
211 orr r1, r1, r2
[all …]
/u-boot/arch/microblaze/cpu/
A Dirq.S13 addik r1, r1, -124
14 swi r2, r1, 4
15 swi r3, r1, 8
16 swi r4, r1, 12
17 swi r5, r1, 16
18 swi r6, r1, 20
19 swi r7, r1, 24
20 swi r8, r1, 28
21 swi r9, r1, 32
22 swi r10, r1, 36
[all …]
A Dstart.S32 add r1, r0, r20
66 addi r1, r1, -4 /* Decrement SP to top of memory */
70 add r5, r0, r1
76 add r1, r0, r3
77 mts rshr, r1
78 addi r1, r1, -4
155 addik r1, r1, -32
156 swi r2, r1, 4
157 swi r3, r1, 8
262 addik r1, r1, 32
[all …]
/u-boot/arch/arm/mach-imx/mx5/
A Dlowlevel_init.S129 ands r1, r1, #0x1
141 ands r1, r1, #0x1
156 3: subs r1, r1, #1
273 add r1, r1, #0x00000F0
323 and r1, r1, #0xfcffffff
324 orr r1, r1, #0x01000000
351 and r1, r1, #0xffffffc0
352 orr r1, r1, #0x0a
371 add r1, r1, #0x00000F0
384 orr r1, r1, #1 << 23
[all …]
/u-boot/post/lib_powerpc/
A Dasm.S22 subi r1, r1, 104
31 addi r1, r1, 104
34 addi r1, r1, 4
45 subi r1, r1, 96
56 addi r1, r1, 96
59 addi r1, r1, 4
80 addi r1, r1, 8
100 addi r1, r1, 8
129 addi r1, r1, 12
182 addi r1, r1, 8
[all …]
/u-boot/arch/arm/mach-uniphier/arm32/
A Ddebug_ll.S35 and r1, r1, #SG_REVISION_TYPE_MASK
36 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
45 orr r1, r1, #1
63 mov r1, #1
68 orr r1, r1, #SC_CLKCTRL_CEN_PERI
83 orr r1, r1, #1
109 orr r1, r1, #SC_CLKCTRL_CEN_PERI
124 orr r1, r1, #1
134 orr r1, r1, #SC_CLKCTRL_CEN_PERI
149 orr r1, r1, #1
[all …]
A Dpsci_smp.S14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
15 orr r1, r1, #CR_I @ Enable ICache
16 bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
27 and r1, r1, #0xff
31 str r0, [r2, r1, lsl #2]
35 cmp r0, r1
/u-boot/board/samsung/smdkc100/
A Dlowlevel_init.S34 ldr r1, =0x9
35 str r1, [r0]
76 ldr r1, =0x00011110
77 str r1, [r8, #0x304]
78 ldr r1, =0x1
79 str r1, [r8, #0x308]
80 ldr r1, =0x00011301
100 ldr r1, =0x80600603
137 mov r1, #0x0
138 str r1, [r0]
[all …]
/u-boot/arch/arm/mach-aspeed/ast2600/
A Dlowlevel_init.S57 str r0, [r1]
59 str r0, [r1]
64 ldr r1, [r1]
66 lsr r1, #0x8
69 cmp r1, #0x0
74 cmp r1, #0x1
79 cmp r1, #0x2
84 cmp r1, #0x3
89 cmp r1, #0x4
135 cmp r1, r0
[all …]
/u-boot/arch/arm/lib/
A Dmemset.S27 1: orr r1, r1, r1, lsl #8
28 orr r1, r1, r1, lsl #16
29 mov r3, r1
39 mov r8, r1
40 mov lr, r1
67 mov r4, r1
68 mov r5, r1
69 mov r6, r1
70 mov r7, r1
71 mov r8, r1
[all …]
A Ddebug.S32 mov r1, #8
37 mov r1, #4
42 mov r1, #2
45 mov r1, #0
46 strb r1, [r3]
49 cmp r1, #10
50 addlt r1, r1, #'0'
51 addge r1, r1, #'a' - 10
76 teqne r1, #0
83 mov r1, r0
[all …]
A Drelocate.S35 ldr r1, =V7M_SCB_BASE
36 str r0, [r1, V7M_SCB_VTOR]
58 stmia r1!, {r2-r8,r10}
60 stmia r1!, {r2-r8,r10}
99 ldr r1, _rel_dyn_start_ofs
101 ldr r1, _rel_dyn_end_ofs
105 and r1, r1, #0xff
106 cmp r1, #R_ARM_RELATIVE
111 ldr r1, [r0]
112 add r1, r1, r4
[all …]
A Dlib1funcs.S325 sub r1, r1, r3
341 sub r1, r1, r3
369 lsrs r1, r1, #1
370 lsls r1, r1, #1
372 lsls r1, r1, #1
383 lsrs r1, r1, #1
384 lsls r1, r1, #1
386 lsls r1, r1, #1
397 lsrs r1, r1, #1
399 lsls r1, r1, #1
[all …]
/u-boot/arch/arm/mach-npcm/npcm7xx/
A Dl2_cache_pl310_init.S22 LDR r1, =0x0
23 STR r1, [r0,#0x100]
28 LDR r1, =0x02050000
29 ORR r1, r1, #(1 << 29) @ Instruction prefetch enable
30 ORR r1, r1, #(1 << 28) @ Data prefetch enable
31 ORR r1, r1, #(1 << 22) @ cache replacement policy
38 LDR r1, =0x00000000
49 LDR r1, =0xFFFF
53 TST r1, #1
57 LDR r1, =0x0
[all …]
/u-boot/board/armltd/integrator/
A Dlowlevel_init.S16 ldr r1,[r0,#OS_CTRL]
17 orr r1,r1,#CMMASK_RESET
18 str r1,[r0,#OS_CTRL]
71 ldr r1, [r0, #OS_INIT]
73 and r3,r1,r2
82 orr r1,r1,r2
85 mov r1, #CMVAL_UNLOCK
111 and r1, r1, #0x20 /* mask SPD bit (5) */
154 mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
174 orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
[all …]
/u-boot/arch/arm/mach-zynq/
A Dlowlevel_init.S13 mrc p15, 0, r1, c1, c0, 2
14 orr r1, r1, #(0x3 << 20)
15 orr r1, r1, #(0x3 << 20)
16 mcr p15, 0, r1, c1, c0, 2
18 fmrx r1, FPEXC
19 orr r1,r1, #(1<<30)
20 fmxr FPEXC, r1
/u-boot/arch/arm/mach-aspeed/ast2500/
A Dlowlevel_init.S19 ldr r1, =SCU_UNLOCK_VALUE
20 str r1, [r0]
24 ldr r1, [r0]
25 orr r1, #0x80
26 str r1, [r0]
30 ldr r1, [r0]
31 tst r1, #(0x1 << 25)
33 movne r1, #(0x1 << 14)
34 strne r1, [r0]
38 mov r1, #0x0
[all …]
/u-boot/arch/arm/mach-orion5x/
A Dlowlevel_init.S181 mov r1, r0
182 mov r1, r1, LSL #9
184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 orr r0, r0, r1
203 mov r1, r0
204 mov r1, r1, LSL #9
205 mov r1, r1, LSR #26
206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 orr r0, r0, r1
226 orr r0, r0, r1
[all …]
/u-boot/arch/arm/mach-mediatek/mt7629/
A Dlowlevel_init.S33 orr r0, r1, #1
64 mov r1, #0xf0
65 str r1, [r2, #4]
66 mov r1, #1
67 str r1, [r2, #0]
69 ldr r1, [r2]
70 orr r1, #1
71 str r1, [r2]
93 cmp r2, r1
97 ldr r1, [r0]
[all …]
/u-boot/arch/arm/mach-rmobile/
A Dlowlevel_init.S13 mov r1, #0x0
14 str r1, [r0]
26 ldr r1, =ICCICR
28 str r2, [r1]
30 adds r1, r1, #4 /* ICCPMR */
31 str r2, [r1]
32 ldr r1, =ICCICR
34 str r2, [r1]
40 ldr r2, [r1, #0xC]
41 str r2, [r1, #0x10]
/u-boot/arch/powerpc/lib/
A Dticks.S32 stwu r1, -16(r1)
34 stw r0, 20(r1) /* Use r0 or GDB will be unhappy */
35 stw r14, 12(r1) /* save used registers */
36 stw r15, 8(r1)
52 lwz r15, 8(r1) /* restore saved registers */
53 lwz r14, 12(r1)
54 lwz r0, 20(r1)
55 addi r1,r1,16
/u-boot/arch/arm/mach-lpc32xx/
A Dlowlevel_init.S23 ldr r1, =0x40004040
24 str r0, [r1]
28 ldr r1, =0x40004058
29 str r0, [r1]
33 ldr r0, [r1]
38 ldr r1, =0x40004044
39 ldr r0, [r1]
41 str r0, [r1]

Completed in 58 milliseconds

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