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Searched refs:rate (Results 1 – 25 of 452) sorted by relevance

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/u-boot/drivers/clk/renesas/
A Dclk-rcar-gen2.c93 return rate; in gen2_clk_get_rate()
106 return rate; in gen2_clk_get_rate()
113 return rate; in gen2_clk_get_rate()
123 return rate; in gen2_clk_get_rate()
131 return rate; in gen2_clk_get_rate()
138 return rate; in gen2_clk_get_rate()
156 return rate; in gen2_clk_get_rate()
163 return rate; in gen2_clk_get_rate()
170 return rate; in gen2_clk_get_rate()
179 return rate; in gen2_clk_get_rate()
[all …]
A Drcar-cpg-lib.c78 u64 rate; in rcar_clk_get_rate64_div_table() local
85 rate = parent_rate / div; in rcar_clk_get_rate64_div_table()
87 __func__, __LINE__, name, parent, div, rate); in rcar_clk_get_rate64_div_table()
89 return rate; in rcar_clk_get_rate64_div_table()
98 div = DIV_ROUND_CLOSEST(parent_rate, rate); in rcar_clk_set_rate64_div_table()
106 __func__, __LINE__, name, parent, div, rate, value); in rcar_clk_set_rate64_div_table()
120 u64 rate = 0; in rcar_clk_get_rate64_rpcd2() local
122 rate = parent_rate / 2; in rcar_clk_get_rate64_rpcd2()
124 __func__, __LINE__, parent, rate); in rcar_clk_get_rate64_rpcd2()
126 return rate; in rcar_clk_get_rate64_rpcd2()
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/u-boot/arch/mips/mach-pic32/
A Dcpu.c29 static ulong rate(int id) in rate() function
34 ulong rate; in rate() local
47 rate = clk_get_rate(&clk); in rate()
51 return rate; in rate()
56 return rate(PB7CLK); in clk_get_cpu_rate()
65 ulong rate; in prefetch_init() local
75 if (rate < 66) in prefetch_init()
77 else if (rate < 133) in prefetch_init()
82 if (rate <= 83) in prefetch_init()
84 else if (rate <= 166) in prefetch_init()
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/u-boot/drivers/clk/rockchip/
A Dclk_rk3568.c354 ulong rate = 0; in rk3568_pmuclk_get_rate() local
388 return rate; in rk3568_pmuclk_get_rate()
537 if (!rate) { in rk3568_armclk_set_clk()
745 return rate; in rk3568_bus_get_clk()
825 return rate; in rk3568_perimid_get_clk()
928 return rate; in rk3568_top_get_clk()
1003 ulong rate; in rk3568_i2c_get_clk() local
1026 return rate; in rk3568_i2c_get_clk()
1030 ulong rate) in rk3568_i2c_set_clk() argument
1854 if (abs(rate - now) < abs(rate - best_rate)) { in rk3568_dclk_vop_set_clk()
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A Dclk_pll.c236 if (rate_table->rate == rate) in rockchip_get_pll_settings()
240 if (rate_table->rate != rate) { in rockchip_get_pll_settings()
257 if (!rate) { in rk3036_pll_set_rate()
263 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
265 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
323 ulong rate; in rk3036_pll_get_rate() local
399 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rk3588_pll_set_rate()
535 rate *= m; in rk3588_pll_get_rate()
544 rate = rate >> s; in rk3588_pll_get_rate()
614 if (ps->rate == rate) in rockchip_get_cpu_settings()
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A Dclk_rk3588.c140 rate = OSC_HZ; in rk3588_center_get_clk()
153 rate = OSC_HZ; in rk3588_center_get_clk()
166 rate = OSC_HZ; in rk3588_center_get_clk()
185 return rate; in rk3588_center_get_clk()
297 return rate; in rk3588_top_get_clk()
350 ulong rate; in rk3588_i2c_get_clk() local
397 return rate; in rk3588_i2c_get_clk()
401 ulong rate) in rk3588_i2c_set_clk() argument
995 if (rate == 400 * MHz || rate == 396 * MHz) in rk3588_aclk_vop_set_clk()
1157 if (abs(rate - now) < abs(rate - best_rate)) { in rk3588_dclk_vop_set_clk()
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A Dclk_rv1126.c76 ulong rate);
327 ulong rate) in rv1126_spi_set_pmuclk() argument
373 ulong rate = 0; in rv1126_pmuclk_get_rate() local
407 return rate; in rv1126_pmuclk_get_rate()
536 if (!rate) { in rv1126_armclk_set_clk()
640 ulong rate) in rv1126_pdbus_set_clk() argument
793 ulong rate) in rv1126_i2c_set_clk() argument
1033 ulong rate) in rv1126_mmc_set_clk() argument
1215 if (abs(rate - now) < abs(rate - best_rate)) { in rv1126_dclk_vop_set_clk()
1414 ulong rate = 0; in rv1126_clk_get_rate() local
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/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c211 rate = rate / val * 18; in scg_apll_pfd_get_rate()
261 rate = rate / val * 18; in scg_spll_pfd_get_rate()
281 rate = rate / (val + 1); in scg_apll_get_rate()
285 rate = rate / (val + 1); in scg_apll_get_rate()
311 rate = rate / (val + 1); in scg_spll_get_rate()
315 rate = rate / (val + 1); in scg_spll_get_rate()
374 rate = rate / (val + 1); in scg_nic_get_rate()
397 rate = rate / (val + 1); in scg_nic_get_rate()
425 rate = rate / (val + 1); in scg_nic_get_rate()
469 rate = rate / (val + 1); in scg_sys_get_rate()
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/u-boot/test/dm/
A Dclk_ccf.c23 long long rate; in dm_test_clk_ccf() local
46 ut_asserteq(rate, 20000000); in dm_test_clk_ccf()
55 ut_asserteq(rate, 20000000); in dm_test_clk_ccf()
64 ut_asserteq(rate, 60000000); in dm_test_clk_ccf()
66 rate = clk_get_rate(clk); in dm_test_clk_ccf()
67 ut_asserteq(rate, 60000000); in dm_test_clk_ccf()
75 rate = clk_get_rate(clk); in dm_test_clk_ccf()
76 ut_asserteq(rate, 80000000); in dm_test_clk_ccf()
90 rate = clk_get_rate(clk); in dm_test_clk_ccf()
99 rate = clk_get_rate(clk); in dm_test_clk_ccf()
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/u-boot/arch/arm/mach-zynq/
A Dclk.c40 ulong rate; in set_cpu_clk_info() local
54 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
56 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
58 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
90 unsigned long rate; in soc_clk_dump() local
97 rate = clk_get_rate(&clk); in soc_clk_dump()
101 if ((rate == (unsigned long)-ENOSYS) || in soc_clk_dump()
102 (rate == (unsigned long)-ENXIO)) in soc_clk_dump()
105 printf("%10s%20lu\n", name, rate); in soc_clk_dump()
/u-boot/drivers/clk/imx/
A Dclk-pll14xx.c57 .rate = (_rate), \
65 .rate = (_rate), \
123 if (rate == rate_table[i].rate) in imx_get_pll_settings()
177 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll1416x_mp_change()
189 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in clk_pll1443x_mpk_change()
190 rate->kdiv != old_kdiv; in clk_pll1443x_mpk_change()
202 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in clk_pll1443x_mp_change()
222 if (!rate) { in clk_pll1416x_set_rate()
252 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
288 if (!rate) { in clk_pll1443x_set_rate()
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/u-boot/drivers/clk/aspeed/
A Dclk_ast2600.c260 uint32_t rate = 0; in ast2600_get_uxclk_in_rate() local
280 return rate; in ast2600_get_uxclk_in_rate()
285 uint32_t rate = 0; in ast2600_get_huxclk_in_rate() local
305 return rate; in ast2600_get_huxclk_in_rate()
334 uint32_t rate = 0; in ast2600_get_sdio_clk_rate() local
359 uint32_t rate = 0; in ast2600_get_uart_clk_rate() local
418 return rate; in ast2600_get_uart_clk_rate()
424 ulong rate = 0; in ast2600_clk_get_rate() local
478 return rate; in ast2600_clk_get_rate()
567 mpll.out = rate; in ast2600_configure_ddr()
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A Dclk_ast2500.c99 u32 rate; in ast2500_get_hclk() local
106 return (rate / axi_div / ahb_div); in ast2500_get_hclk()
144 ulong rate; in ast2500_clk_get_rate() local
152 rate = ast2500_get_hpll_rate(clkin, in ast2500_clk_get_rate()
156 rate = ast2500_get_mpll_rate(clkin, in ast2500_clk_get_rate()
164 rate = ast2500_get_hpll_rate(clkin, in ast2500_clk_get_rate()
167 rate = rate / apb_div; in ast2500_clk_get_rate()
178 rate = ast2500_get_hpll_rate(clkin, in ast2500_clk_get_rate()
181 rate = rate / apb_div; in ast2500_clk_get_rate()
204 return rate; in ast2500_clk_get_rate()
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/u-boot/drivers/cpu/
A Dat91_cpu.c81 ulong rate; in at91_cpu_probe() local
88 rate = clk_get_rate(&clk); in at91_cpu_probe()
89 if (!rate) in at91_cpu_probe()
91 plat->cpufreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
97 rate = clk_get_rate(&clk); in at91_cpu_probe()
98 if (!rate) in at91_cpu_probe()
100 plat->mckfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
106 rate = clk_get_rate(&clk); in at91_cpu_probe()
107 if (!rate) in at91_cpu_probe()
109 plat->xtalfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_agilex.c24 ulong rate; in cm_get_rate_dm() local
38 rate = clk_get_rate(&clk); in cm_get_rate_dm()
42 if ((rate == (unsigned long)-ENOSYS) || in cm_get_rate_dm()
43 (rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
44 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
46 __func__, id, rate); in cm_get_rate_dm()
50 return rate; in cm_get_rate_dm()
A Dclock_manager_n5x.c23 ulong rate; in cm_get_rate_dm() local
37 rate = clk_get_rate(&clk); in cm_get_rate_dm()
41 if ((rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
42 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
44 __func__, id, rate); in cm_get_rate_dm()
48 return rate; in cm_get_rate_dm()
/u-boot/drivers/clk/meson/
A Dg12a.c286 return rate; in meson_div_get_rate()
299 if (current_rate == rate) in meson_div_set_rate()
694 ulong rate; in meson_pll_get_rate() local
739 rate -= frac_rate; in meson_pll_get_rate()
741 rate += frac_rate; in meson_pll_get_rate()
779 ulong rate; in meson_clk_get_rate_by_id() local
783 rate = XTAL_RATE; in meson_clk_get_rate_by_id()
859 return rate; in meson_clk_get_rate_by_id()
900 if (current_rate == rate) in meson_clk_set_rate_by_id()
930 rate, current_rate); in meson_clk_set_rate_by_id()
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/u-boot/arch/arm/mach-nexell/
A Dclock.c527 return rate; in core_get_rate()
532 return clk->rate; in core_set_rate()
557 return rate; in clk_divide()
570 ret = rate / div; in clk_divide()
650 rate = pll->clk.rate; in clk_round_rate()
653 if (!rate) in clk_round_rate()
657 rate = clk_divide(rate, request, 2, &div[i]); in clk_round_rate()
673 rate_hz = rate; in clk_round_rate()
697 rate); in clk_round_rate()
702 return clk->rate; in clk_round_rate()
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/u-boot/drivers/clk/ti/
A Dclk-am3-dpll-x2.c23 unsigned long rate; in clk_ti_am3_dpll_x2_get_rate() local
25 rate = clk_get_rate(&priv->parent); in clk_ti_am3_dpll_x2_get_rate()
26 if (IS_ERR_VALUE(rate)) in clk_ti_am3_dpll_x2_get_rate()
27 return rate; in clk_ti_am3_dpll_x2_get_rate()
29 rate *= 2; in clk_ti_am3_dpll_x2_get_rate()
30 dev_dbg(clk->dev, "rate=%ld\n", rate); in clk_ti_am3_dpll_x2_get_rate()
31 return rate; in clk_ti_am3_dpll_x2_get_rate()
A Dclk-divider.c72 ulong rate) in _div_round_up() argument
92 ulong rate) in _div_round() argument
112 if (!rate) in clk_ti_divider_best_div()
113 rate = 1; in clk_ti_divider_best_div()
137 if ((rate * i) == parent_rate) { in clk_ti_divider_best_div()
140 rate, rate, i); in clk_ti_divider_best_div()
145 MULT_ROUND_UP(rate, i)); in clk_ti_divider_best_div()
150 if (r <= rate && r > best_rate) { in clk_ti_divider_best_div()
154 if (best_rate == rate) in clk_ti_divider_best_div()
215 ulong rate, parent_rate; in clk_ti_divider_get_rate() local
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/u-boot/drivers/clk/
A Dclk_pic32.c192 do_div(frac, rate); in pic32_set_refclk()
288 u64 rate; in pic32_get_mpll_rate() local
297 do_div(rate, odiv1); in pic32_get_mpll_rate()
298 do_div(rate, odiv2); in pic32_get_mpll_rate()
300 return (ulong)rate; in pic32_get_mpll_rate()
325 ulong rate, pll_hz; in pic32_clk_init() local
337 if (rate) in pic32_clk_init()
348 ulong rate; in pic32_get_rate() local
364 rate = 0; in pic32_get_rate()
368 return rate; in pic32_get_rate()
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A Dclk-composite.c54 struct clk *rate = composite->rate; in clk_composite_recalc_rate() local
56 if (rate && rate_ops) in clk_composite_recalc_rate()
57 return rate_ops->get_rate(rate); in clk_composite_recalc_rate()
67 struct clk *clk_rate = composite->rate; in clk_composite_set_rate()
69 if (rate && rate_ops) in clk_composite_set_rate()
105 struct clk *rate, in clk_register_composite() argument
128 if (rate && rate_ops) { in clk_register_composite()
134 composite->rate = rate; in clk_register_composite()
136 rate->data = (ulong)composite; in clk_register_composite()
161 if (composite->rate) in clk_register_composite()
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A Dclk-hsdk-cgu.c194 const u32 rate; member
261 unsigned long rate,
426 u64 rate; in pll_get() local
451 do_div(rate, idiv * odiv); in pll_get()
453 return rate; in pll_get()
463 if (pll_cfg[0].rate == 0) in hsdk_pll_round_rate()
469 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate)) in hsdk_pll_round_rate()
479 unsigned long rate, in hsdk_pll_comm_update_rate() argument
499 unsigned long rate, in hsdk_pll_core_update_rate() argument
582 ret = pll_set(sclk, rate); in cpu_clk_set()
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/u-boot/drivers/i2c/
A Dsynquacer_i2c.c56 #define BUS_CLK_FR(rate) (((rate) / 20000000) + 1) argument
61 #define CLK_MASTER_STD(rate) \ argument
64 #define CLK_MASTER_FAST(rate) \ argument
69 #define CCR_CS_STD_MAX_18M(rate) \ argument
70 ((CLK_MASTER_STD(rate) - 65) \
77 #define CCR_CS_FAST_MAX_18M(rate) \ argument
78 ((CLK_MASTER_FAST(rate) - 1) \
86 #define CCR_CS_STD_MIN_18M(rate) \ argument
87 ((CLK_MASTER_STD(rate) - 1) \
91 #define CSR_CS_STD_MIN_18M(rate) \ argument
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/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.c173 diff = rate; in peri_clk_set_rate()
184 div = ref->clk.rate / rate; in peri_clk_set_rate()
195 c->rate = new_rate; in peri_clk_set_rate()
201 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
243 c->rate = c->parent->rate / c->div; in peri_clk_get_rate()
245 c->parent->rate, div, c->sel, c->rate); in peri_clk_get_rate()
247 return c->rate; in peri_clk_get_rate()
326 return c->rate; in ccu_clk_get_rate()
386 return c->rate; in bus_clk_get_rate()
481 unsigned long rate; in clk_get_rate() local
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