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Searched refs:receive (Results 1 – 25 of 53) sorted by relevance

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/u-boot/include/
A Ddma-uclass.h100 int (*receive)(struct dma *dma, void **dst, void *metadata); member
/u-boot/doc/device-tree-bindings/misc/misc/
A Dgdsys,io-endpoint.txt4 that allows interconnected gdsys devices to send and receive data over the
/u-boot/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/
A Ducc.txt7 - rx-clock-name: the UCC receive clock source
20 - rx-clock : represents the UCC receive clock source.
/u-boot/doc/device-tree-bindings/mailbox/
A Dk3-secure-proxy.txt6 has different address space that can be used to send or receive messages.
/u-boot/doc/device-tree-bindings/firmware/
A Dti,j721e-dm-sci.txt9 "rx" - Mailbox corresponding to receive path
A Dti,sci.txt29 "rx" - Mailbox corresponding to receive path
/u-boot/drivers/dma/
A Ddma-uclass.c179 if (!ops->receive) in dma_receive()
182 return ops->receive(dma, dst, metadata); in dma_receive()
A Dsandbox-dma-test.c238 .receive = sandbox_dma_receive,
/u-boot/doc/device-tree-bindings/serial/
A Domap_serial.txt21 - dma-names : "rx" for receive channel, "tx" for transmit channel.
/u-boot/doc/device-tree-bindings/net/
A Dethernet.txt63 - rx-fifo-depth: the size of the controller's receive fifo in bytes. This
64 is used for components that can have configurable receive fifo sizes,
A Dsnps,dwc-qos-ethernet.txt30 The EQOS receive path clock. The HW signal name is clk_rx_i.
34 In cases where the PHY clock is directly fed into the EQOS receive path
A Daltera_tse.txt20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
/u-boot/doc/usage/cmd/
A Dloadx.rst51 Sending helloworld.efi, 24 blocks: Give your local XMODEM receive command now.
/u-boot/arch/arm/dts/
A Dimx6q-hummingboard-som-v15.dts59 fsl,receive-eq-mdB = <3000>;
A Dimx6q-hummingboard.dts59 fsl,receive-eq-mdB = <3000>;
A Dimx6q-hummingboard-emmc-som-v15.dts60 fsl,receive-eq-mdB = <3000>;
/u-boot/arch/mips/dts/
A Dmrvl,octeon-nic23.dts223 * receive channels.
278 * receive channels.
/u-boot/doc/device-tree-bindings/reset/
A Dreset.txt8 Hardware blocks typically receive a reset signal. This signal is generated by
/u-boot/doc/
A DREADME.tee41 driver. The main job for the driver is to receive requests from the
A DREADME.mpc85xx6 be able to receive control after a single step or breakpoint:
/u-boot/net/
A DKconfig258 int "Number of receive packet buffers"
261 Defines the number of Ethernet receive buffers. On some Ethernet
/u-boot/lib/efi_selftest/
A Defi_selftest_snp.c369 ret = net->receive(net, NULL, &buffer_size, &buffer, in execute()
/u-boot/doc/device-tree-bindings/spi/
A Dspi-bus.txt67 Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
/u-boot/doc/device-tree-bindings/gpio/
A Dintel,x86-broadwell-pinctrl.txt42 But missing pins will receive the default configuration.
/u-boot/Licenses/
A Dgpl-2.0.txt24 this service if you wish), that you receive source code or can get it
35 you have. You must make sure that they, too, receive or can get the
80 source code as you receive it, in any medium, provided that you
206 all those who receive copies directly or indirectly through you, then

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