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Searched refs:reg_base (Results 1 – 25 of 48) sorted by relevance

12

/u-boot/drivers/ata/
A Dahci_sunxi.c19 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
24 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
27 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
28 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
31 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
35 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
40 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
44 reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); in sunxi_ahci_phy_init()
54 setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); in sunxi_ahci_phy_init()
58 reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); in sunxi_ahci_phy_init()
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/u-boot/drivers/watchdog/
A Dmeson_gxbb_wdt.c29 void __iomem *reg_base; member
42 writel(timeout_ms, data->reg_base + GXBB_WDT_TCNT_REG); in amlogic_wdt_set_timeout()
51 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN, in amlogic_wdt_stop()
52 data->reg_base + GXBB_WDT_CTRL_REG); in amlogic_wdt_stop()
61 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN, in amlogic_wdt_start()
62 data->reg_base + GXBB_WDT_CTRL_REG); in amlogic_wdt_start()
71 writel(0, data->reg_base + GXBB_WDT_RSET_REG); in amlogic_wdt_reset()
80 writel(0, data->reg_base + GXBB_WDT_CTRL_SYS_RESET_NOW); in amlogic_wdt_expire_now()
90 data->reg_base = dev_remap_addr(dev); in amlogic_wdt_probe()
91 if (!data->reg_base) in amlogic_wdt_probe()
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/u-boot/drivers/spi/
A Dcadence_qspi_apb.c49 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
51 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
57 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
59 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
66 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_dac_mode_enable()
161 if (CQSPI_REG_IS_IDLE(reg_base)) in cadence_qspi_wait_idle()
376 if (!cadence_qspi_wait_idle(reg_base)) in cadence_qspi_apb_exec_flash_cmd()
459 void *reg_base = priv->regbase; in cadence_qspi_apb_command_read() local
553 void *reg_base = priv->regbase; in cadence_qspi_apb_command_write() local
592 writel(wr_data, reg_base + in cadence_qspi_apb_command_write()
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A Dcadence_qspi.h192 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
193 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
196 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
197 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
269 void cadence_qspi_apb_dac_mode_enable(void *reg_base);
289 void cadence_qspi_apb_chipselect(void *reg_base,
291 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
292 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
294 void cadence_qspi_apb_delay(void *reg_base,
298 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
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A Datmel_spi.c127 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_claim_bus() local
147 writel(csrx, &reg_base->csr[cs]); in atmel_spi_claim_bus()
154 writel(mode, &reg_base->mr); in atmel_spi_claim_bus()
156 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); in atmel_spi_claim_bus()
206 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_xfer() local
248 readl(&reg_base->rdr); in atmel_spi_xfer()
252 status = readl(&reg_base->sr); in atmel_spi_xfer()
262 writel(value, &reg_base->tdr); in atmel_spi_xfer()
267 value = readl(&reg_base->rdr); in atmel_spi_xfer()
280 wait_for_bit_le32(&reg_base->sr, in atmel_spi_xfer()
/u-boot/arch/arm/mach-uniphier/clk/
A Dpll.h14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
19 int uniphier_ld20_dspll_init(unsigned long reg_base);
A Dpll-base-ld20.c32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument
35 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_init()
63 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument
65 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_ssc_en()
75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
77 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_set_regi()
88 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument
90 void __iomem *base = sc_base + reg_base; in uniphier_ld20_vpll27_init()
108 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument
110 void __iomem *base = sc_base + reg_base; in uniphier_ld20_dspll_init()
/u-boot/drivers/mmc/
A Dkona_sdhci.c82 void *reg_base; in kona_sdhci_init() local
92 reg_base = (void *)CONFIG_SYS_SDIO_BASE0; in kona_sdhci_init()
93 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, in kona_sdhci_init()
97 reg_base = (void *)CONFIG_SYS_SDIO_BASE1; in kona_sdhci_init()
98 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, in kona_sdhci_init()
102 reg_base = (void *)CONFIG_SYS_SDIO_BASE2; in kona_sdhci_init()
103 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, in kona_sdhci_init()
107 reg_base = (void *)CONFIG_SYS_SDIO_BASE3; in kona_sdhci_init()
108 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, in kona_sdhci_init()
122 host->ioaddr = reg_base; in kona_sdhci_init()
A Dowl_mmc.c108 void *reg_base; member
146 writel(512, priv->reg_base + OWL_REG_SD_BUF_SIZE); in owl_mmc_prepare_data()
154 owl_dma_config(priv, (ulong) priv->reg_base + in owl_mmc_prepare_data()
159 owl_dma_config(priv, buf, (ulong) priv->reg_base + in owl_mmc_prepare_data()
214 writel(mode, priv->reg_base + OWL_REG_SD_CTL); in owl_mmc_send_cmd()
264 clrbits_le32(priv->reg_base + OWL_REG_SD_CTL, in owl_mmc_send_cmd()
275 reg = readl(priv->reg_base + OWL_REG_SD_CTL); in owl_mmc_clk_set()
292 priv->reg_base + OWL_REG_SD_CTL); in owl_mmc_clk_set()
323 reg = readl(priv->reg_base + OWL_REG_SD_EN); in owl_mmc_set_ios()
330 writel(reg, priv->reg_base + OWL_REG_SD_EN); in owl_mmc_set_ios()
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A Ddavinci_mmc.c31 struct davinci_mmc_regs *reg_base; /* Register base address */ member
50 struct davinci_mmc_regs *regs = host->reg_base;
156 volatile struct davinci_mmc_regs *regs = host->reg_base;
349 struct davinci_mmc_regs *regs = host->reg_base;
385 struct davinci_mmc_regs *regs = host->reg_base;
392 struct davinci_mmc_regs *regs = host->reg_base;
484 priv->reg_base = plat->reg_base;
509 plat->reg_base = dev_read_addr_ptr(dev);
/u-boot/drivers/net/pfe_eth/
A Dpfe_mdio.c22 void *reg_base = bus->priv; in pfe_write_addr() local
33 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
48 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_write_addr()
56 void *reg_base = bus->priv; in pfe_phy_read() local
81 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
96 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_read()
101 val = (u16)readl(reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
111 void *reg_base = bus->priv; in pfe_phy_write() local
135 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_write()
150 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_write()
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/u-boot/drivers/usb/musb-new/
A Dda8xx.c70 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
103 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
147 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_interrupt()
157 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init() local
178 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); in da8xx_musb_init()
199 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
209 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
220 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable() local
222 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, in da8xx_musb_disable()
225 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_disable()
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A Dam35x.c98 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
105 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
122 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
125 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
128 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
230 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
287 int drvvbus = musb_readl(reg_base, USB_STAT_REG); in am35x_musb_interrupt()
344 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_interrupt()
385 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_init() local
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A Dmusb_dsps.c162 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
175 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
192 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
195 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
198 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
299 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
399 dsps_writel(reg_base, wrp->eoi, 1); in dsps_interrupt()
426 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_init() local
442 rev = dsps_readl(reg_base, wrp->revision); in dsps_musb_init()
463 val = dsps_readl(reg_base, wrp->phy_utmi); in dsps_musb_init()
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/u-boot/drivers/pci_endpoint/
A Dpcie-cadence.h231 void __iomem *reg_base; member
239 writeb(value, pcie->reg_base + reg); in cdns_pcie_writeb()
244 writew(value, pcie->reg_base + reg); in cdns_pcie_writew()
249 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
254 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
261 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writeb()
267 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writew()
273 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writel()
297 return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readb()
302 return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readw()
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/u-boot/drivers/phy/rockchip/
A Dphy-rockchip-pcie.c65 void *reg_base; member
77 writel(reg, priv->reg_base + priv->data->pcie_conf); in phy_wr_cfg()
84 writel(reg, priv->reg_base + priv->data->pcie_conf); in phy_wr_cfg()
91 writel(reg, priv->reg_base + priv->data->pcie_conf); in phy_wr_cfg()
109 writel(reg, priv->reg_base + priv->data->pcie_conf); in rockchip_pcie_phy_power_on()
114 writel(reg, priv->reg_base + priv->data->pcie_laneoff); in rockchip_pcie_phy_power_on()
117 ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status, in rockchip_pcie_phy_power_on()
131 ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status, in rockchip_pcie_phy_power_on()
144 writel(reg, priv->reg_base + priv->data->pcie_conf); in rockchip_pcie_phy_power_on()
173 writel(reg, priv->reg_base + priv->data->pcie_laneoff); in rockchip_pcie_phy_power_off()
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A Dphy-rockchip-inno-usb2.c64 void *reg_base; member
69 static inline int property_enable(void *reg_base, in property_enable() argument
78 return writel(val, reg_base + reg->offset); in property_enable()
81 static inline bool property_enabled(void *reg_base, in property_enabled() argument
87 orig = readl(reg_base + reg->offset); in property_enabled()
109 property_enable(priv->reg_base, &port_cfg->phy_sus, false); in rockchip_usb2phy_power_on()
123 property_enable(priv->reg_base, &port_cfg->phy_sus, true); in rockchip_usb2phy_power_off()
211 property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true); in rockchip_usb2phy_clk_enable()
233 property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false); in rockchip_usb2phy_clk_disable()
252 if (IS_ERR(priv->reg_base)) in rockchip_usb2phy_probe()
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A Dphy-rockchip-typec.c343 void __iomem *reg_base; member
399 writel(0x830, priv->reg_base + PMA_CMN_CTRL1); in rockchip_tcphy_cfg_24m()
423 priv->reg_base + usb3_pll_cfg[i].addr); in rockchip_tcphy_cfg_usb3_pll()
429 writel(0x7799, priv->reg_base + TX_PSC_A0(lane)); in rockchip_tcphy_tx_usb3_cfg_lane()
430 writel(0x7798, priv->reg_base + TX_PSC_A1(lane)); in rockchip_tcphy_tx_usb3_cfg_lane()
431 writel(0x5098, priv->reg_base + TX_PSC_A2(lane)); in rockchip_tcphy_tx_usb3_cfg_lane()
432 writel(0x5098, priv->reg_base + TX_PSC_A3(lane)); in rockchip_tcphy_tx_usb3_cfg_lane()
440 writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane)); in rockchip_tcphy_rx_usb3_cfg_lane()
441 writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane)); in rockchip_tcphy_rx_usb3_cfg_lane()
677 priv->reg_base = dev_read_addr_ptr(dev); in rockchip_tcphy_probe()
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/u-boot/drivers/mtd/nand/raw/
A Docteontx_bch.c83 writeq(1, bch->reg_base + BCH_CTL); in bch_reset()
89 writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C); in bch_disable()
90 writeq(~0ull, bch->reg_base + BCH_ERR_INT); in bch_disable()
96 return readq(bch->reg_base + BCH_BIST_RESULT); in bch_check_bist_status()
174 bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, in octeontx_pci_bchpf_probe()
178 debug("%s: base address: %p\n", __func__, bch->reg_base); in octeontx_pci_bchpf_probe()
362 debug("%s: reg base: %p\n", __func__, vf->reg_base); in octeontx_pci_bchvf_probe()
371 ctl.u = readq(vf->reg_base + BCH_VQX_CTL(0)); in octeontx_pci_bchvf_probe()
377 writeq(cbuf.u, vf->reg_base + BCH_VQX_CMD_BUF(0)); in octeontx_pci_bchvf_probe()
379 writeq(ctl.u, vf->reg_base + BCH_VQX_CTL(0)); in octeontx_pci_bchvf_probe()
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A Docteontx_bch.h42 void __iomem *reg_base; member
52 void __iomem *reg_base; member
117 writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0)); in octeontx_bch_write_doorbell()
/u-boot/drivers/net/
A Dmdio_mux_mmioreg.c82 phys_addr_t reg_base, reg_size; in mdio_mux_mmioreg_probe() local
86 reg_base = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &reg_size); in mdio_mux_mmioreg_probe()
87 if (reg_base == FDT_ADDR_T_NONE) in mdio_mux_mmioreg_probe()
108 priv->phys = reg_base; in mdio_mux_mmioreg_probe()
112 debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask); in mdio_mux_mmioreg_probe()
/u-boot/drivers/net/octeontx2/
A Dcgx.c88 reg_addr = lmac->cgx->reg_base + in cgx_lmac_mac_filter_clear()
97 reg_addr = lmac->cgx->reg_base + in cgx_lmac_mac_filter_clear()
119 reg_addr = lmac->cgx->reg_base + in cgx_lmac_mac_filter_setup()
127 reg_addr = lmac->cgx->reg_base + in cgx_lmac_mac_filter_setup()
221 cgx->cgx_id, cgx->reg_base); in cgx_lmac_init()
256 cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, in cgx_probe()
259 cgx->cgx_id = ((u64)(cgx->reg_base) >> 24) & 0x7; in cgx_probe()
261 debug("%s CGX BAR %p, id: %d\n", __func__, cgx->reg_base, in cgx_probe()
276 __func__, cgx->reg_base, cgx->cgx_id); in cgx_remove()
A Dcgx.h62 void __iomem *reg_base; member
71 writeq(val, cgx->reg_base + CMR_SHIFT(lmac) + offset); in cgx_write()
76 return readq(cgx->reg_base + CMR_SHIFT(lmac) + offset); in cgx_read()
/u-boot/drivers/mailbox/
A Dstm32-ipcc.c39 void __iomem *reg_base; member
115 ipcc->reg_base = (void __iomem *)addr; in stm32_ipcc_probe()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
140 ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); in stm32_ipcc_probe()
/u-boot/drivers/clk/at91/
A Dcompat.c26 struct at91_pmc *reg_base; member
53 plat->reg_base = dev_read_addr_ptr(dev); in at91_pmc_core_probe()
200 struct at91_pmc *pmc = plat->reg_base; in main_osc_clk_enable()
241 struct at91_pmc *pmc = plat->reg_base; in plla_clk_enable()
287 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate()
306 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_set_rate()
410 struct at91_pmc *pmc = plat->reg_base; in system_clk_enable()
492 struct at91_pmc *pmc = plat->reg_base; in periph_clk_enable()
561 struct at91_pmc *pmc = plat->reg_base; in utmi_clk_enable()
690 struct at91_pmc *pmc = plat->reg_base; in sama5d4_h32mx_clk_get_rate()
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