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Searched refs:regs (Results 1 – 25 of 608) sorted by relevance

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/u-boot/board/cavium/thunderx/
A Datf.c25 regs.regs[1] = offset; in atf_read_mmc()
26 regs.regs[2] = size; in atf_read_mmc()
31 return regs.regs[0]; in atf_read_mmc()
38 regs.regs[1] = offset; in atf_read_nor()
39 regs.regs[2] = size; in atf_read_nor()
44 return regs.regs[0]; in atf_read_nor()
54 return regs.regs[0]; in atf_get_pcount()
62 regs.regs[2] = index; in atf_get_part()
66 return regs.regs[0]; in atf_get_part()
78 return regs.regs[0]; in atf_erase_nor()
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/u-boot/test/lib/
A Defi_image_region.c18 regs = calloc(sizeof(*regs) + in lib_test_efi_image_region_add()
20 ut_assert(regs); in lib_test_efi_image_region_add()
22 regs->max = UT_REG_CAPACITY; in lib_test_efi_image_region_add()
24 ut_asserteq(0, regs->num); in lib_test_efi_image_region_add()
28 ut_asserteq(0, regs->num); in lib_test_efi_image_region_add()
32 ut_asserteq(1, regs->num); in lib_test_efi_image_region_add()
36 ut_asserteq(2, regs->num); in lib_test_efi_image_region_add()
65 free(regs); in lib_test_efi_image_region_add()
76 regs = calloc(sizeof(*regs) + in lib_test_efi_image_region_sort()
78 ut_assert(regs); in lib_test_efi_image_region_sort()
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/u-boot/board/Marvell/octeontx2/
A Dsmc.c21 regs.regs[0] = OCTEONTX2_DRAM_SIZE; in smc_dram_size()
22 regs.regs[1] = node; in smc_dram_size()
25 return regs.regs[0]; in smc_dram_size()
32 regs.regs[0] = OCTEONTX2_DISABLE_RVU_LFS; in smc_disable_rvu_lfs()
33 regs.regs[1] = node; in smc_disable_rvu_lfs()
36 return regs.regs[0]; in smc_disable_rvu_lfs()
43 regs.regs[0] = OCTEONTX2_CONFIG_OOO; in smc_configure_ooo()
44 regs.regs[1] = val; in smc_configure_ooo()
47 return regs.regs[0]; in smc_configure_ooo()
54 regs.regs[0] = OCTEONTX2_FSAFE_PR_BOOT_SUCCESS; in smc_flsf_fw_booted()
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/u-boot/arch/arm/cpu/armv8/
A Dfwcall.c37 : "+m" (args->regs[0]), "+m" (args->regs[1]), in hvc_call()
38 "+m" (args->regs[2]), "+m" (args->regs[3]) in hvc_call()
39 : "m" (args->regs[4]), "m" (args->regs[5]), in hvc_call()
70 : "+m" (args->regs[0]), "+m" (args->regs[1]), in smc_call()
71 "+m" (args->regs[2]), "+m" (args->regs[3]) in smc_call()
72 : "m" (args->regs[4]), "m" (args->regs[5]), in smc_call()
91 regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET; in psci_system_reset()
106 regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2; in psci_system_reset2()
107 regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level; in psci_system_reset2()
108 regs.regs[2] = cookie; in psci_system_reset2()
[all …]
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dtraps.c60 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); in show_regs()
62 regs->msr, regs->msr & MSR_EE ? 1 : 0, in show_regs()
63 regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, in show_regs()
64 regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, in show_regs()
81 show_regs(regs); in _exception()
119 show_regs(regs); in MachineCheckException()
126 show_regs(regs); in AlignmentException()
133 show_regs(regs); in ProgramCheckException()
140 show_regs(regs); in SoftEmuException()
149 regs->nip, regs->msr, regs->trap); in UnknownException()
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/u-boot/arch/arm/mach-meson/
A Dsm.c55 regs.regs[0] = FN_EFUSE_READ; in meson_sm_read_efuse()
56 regs.regs[1] = offset; in meson_sm_read_efuse()
57 regs.regs[2] = size; in meson_sm_read_efuse()
61 if (regs.regs[0] == 0) in meson_sm_read_efuse()
66 return regs.regs[0]; in meson_sm_read_efuse()
78 regs.regs[1] = offset; in meson_sm_write_efuse()
79 regs.regs[2] = size; in meson_sm_write_efuse()
83 return regs.regs[0]; in meson_sm_write_efuse()
96 regs.regs[0] = FN_CHIP_ID; in meson_sm_get_serial()
97 regs.regs[1] = 0; in meson_sm_get_serial()
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/u-boot/arch/powerpc/cpu/mpc83xx/
A Dtraps.c58 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); in show_regs()
60 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
61 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
81 show_regs(regs); in _exception()
125 regs->nip = fixup; in MachineCheckException()
154 show_regs(regs); in MachineCheckException()
168 show_regs(regs); in AlignmentException()
179 show_regs(regs); in ProgramCheckException()
190 show_regs(regs); in SoftEmuException()
203 regs->nip, regs->msr, regs->trap); in UnknownException()
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A Dserdes.c54 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
56 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); in fsl_setup_serdes()
59 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
61 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
81 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
83 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()
86 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
89 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
95 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); in fsl_setup_serdes()
99 out_be32(regs + FSL_SRDSCR4_OFFS, tmp); in fsl_setup_serdes()
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/u-boot/arch/arc/lib/
A Dinterrupts.c66 regs->ret, regs->blink, regs->status32); in show_regs()
67 printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25); in show_regs()
69 regs->sp, regs->fp); in show_regs()
71 regs->lp_end, regs->lp_count); in show_regs()
78 if (regs) in bad_mode()
87 bad_mode(regs); in do_memory_error()
93 bad_mode(regs); in do_instruction_error()
99 bad_mode(regs); in do_machine_check_fault()
111 bad_mode(regs); in do_itlb_miss()
117 bad_mode(regs); in do_dtlb_miss()
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/u-boot/arch/powerpc/cpu/mpc85xx/
A Dtraps.c92 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); in show_regs()
94 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
95 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
117 show_regs(regs); in _exception()
184 show_regs(regs); in MachineCheckException()
208 show_regs(regs); in AlignmentException()
222 show_regs(regs); in ProgramCheckException()
257 regs->nip, regs->msr, regs->trap); in UnknownException()
273 regs->nip, regs->msr, regs->trap); in ExtIntException()
276 show_regs(regs); in ExtIntException()
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/u-boot/arch/riscv/include/asm/
A Dptrace.h57 #define user_mode(regs) (((regs)->sstatus & SR_PS) == 0) argument
60 #define GET_IP(regs) ((regs)->sepc) argument
61 #define SET_IP(regs, val) (GET_IP(regs) = (val)) argument
70 SET_IP(regs, val); in instruction_pointer_set()
73 #define profile_pc(regs) instruction_pointer(regs) argument
76 #define GET_USP(regs) ((regs)->sp) argument
77 #define SET_USP(regs, val) (GET_USP(regs) = (val)) argument
86 SET_USP(regs, val); in user_stack_pointer_set()
90 #define GET_FP(regs) ((regs)->s0) argument
91 #define SET_FP(regs, val) (GET_FP(regs) = (val)) argument
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/u-boot/arch/mips/lib/
A Dasm-offsets.c20 OFFSET(PT_R0, pt_regs, regs[0]); in output_ptreg_defines()
21 OFFSET(PT_R1, pt_regs, regs[1]); in output_ptreg_defines()
22 OFFSET(PT_R2, pt_regs, regs[2]); in output_ptreg_defines()
23 OFFSET(PT_R3, pt_regs, regs[3]); in output_ptreg_defines()
24 OFFSET(PT_R4, pt_regs, regs[4]); in output_ptreg_defines()
25 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
26 OFFSET(PT_R6, pt_regs, regs[6]); in output_ptreg_defines()
27 OFFSET(PT_R7, pt_regs, regs[7]); in output_ptreg_defines()
28 OFFSET(PT_R8, pt_regs, regs[8]); in output_ptreg_defines()
29 OFFSET(PT_R9, pt_regs, regs[9]); in output_ptreg_defines()
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/u-boot/drivers/video/rockchip/
A Drk_mipi.c83 uintptr_t regs = priv->regs; in rk_mipi_dsi_enable() local
141 rk_mipi_dsi_write(regs, LP_CMD_EN, 1); in rk_mipi_dsi_enable()
142 rk_mipi_dsi_write(regs, LP_HFP_EN, 1); in rk_mipi_dsi_enable()
143 rk_mipi_dsi_write(regs, LP_VACT_EN, 1); in rk_mipi_dsi_enable()
144 rk_mipi_dsi_write(regs, LP_VFP_EN, 1); in rk_mipi_dsi_enable()
145 rk_mipi_dsi_write(regs, LP_VBP_EN, 1); in rk_mipi_dsi_enable()
146 rk_mipi_dsi_write(regs, LP_VSA_EN, 1); in rk_mipi_dsi_enable()
165 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); in rk_mipi_dsi_enable()
200 uintptr_t regs = priv->regs; in rk_mipi_phy_enable() local
225 rk_mipi_dsi_write(regs, PHY_RSTZ, 0); in rk_mipi_phy_enable()
[all …]
/u-boot/drivers/spmi/
A Dspmi-sandbox.c71 regs[0x8].value &= ~0x1; in sandbox_spmi_write()
77 regs[off].value = val & regs[off].access_mask; in sandbox_spmi_write()
99 return regs[off].value; in sandbox_spmi_read()
102 return regs[off].value; in sandbox_spmi_read()
121 regs[4].value = 0x10; in sandbox_spmi_probe()
123 regs[5].value = 0x5; in sandbox_spmi_probe()
124 regs[8].access_mask = 0x81; in sandbox_spmi_probe()
128 regs[0x41].access_mask = 7; in sandbox_spmi_probe()
132 regs[0x42].value = 0x4; in sandbox_spmi_probe()
135 regs[0x45].value = 0x1; in sandbox_spmi_probe()
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/u-boot/drivers/ddr/fsl/
A Darm_ddr_gen3.c68 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
69 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
119 if (regs->ddr_wrlvl_cntl_2) in fsl_ddr_set_memctl_regs()
121 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
150 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
152 regs->debug[i]); in fsl_ddr_set_memctl_regs()
172 temp_sdram_cfg = regs->ddr_sdram_cfg; in fsl_ddr_set_memctl_regs()
204 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
209 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
[all …]
A Dfsl_ddr_gen4.c116 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
118 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
119 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
129 (regs->cs[i].config & in fsl_ddr_set_memctl_regs()
216 if (regs->ddr_wrlvl_cntl_2) in fsl_ddr_set_memctl_regs()
218 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()
253 regs->ddr_sdram_rcw_2 & ~0xf0); in fsl_ddr_set_memctl_regs()
263 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
265 i+1, regs->debug[i]); in fsl_ddr_set_memctl_regs()
328 temp32 = regs->ddr_sdram_cfg; in fsl_ddr_set_memctl_regs()
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/u-boot/arch/mips/include/asm/
A Dptrace.h27 unsigned long regs[32]; member
48 return regs->regs[31]; in kernel_stack_pointer()
56 static inline void instruction_pointer_set(struct pt_regs *regs, in instruction_pointer_set() argument
59 regs->cp0_epc = val; in instruction_pointer_set()
81 return *(unsigned long *)((unsigned long)regs + offset); in regs_get_register()
87 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) argument
89 #define instruction_pointer(regs) ((regs)->cp0_epc) argument
90 #define profile_pc(regs) instruction_pointer(regs) argument
96 return regs->regs[29]; in user_stack_pointer()
99 static inline void user_stack_pointer_set(struct pt_regs *regs, in user_stack_pointer_set() argument
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/u-boot/arch/powerpc/lib/
A Dkgdb.c90 regs->nip += 4; in kgdb_enter()
100 kdp->regs[0].val = regs->nip; in kgdb_enter()
103 kdp->regs[1].val = regs->gpr[SP_REGNUM]; in kgdb_enter()
133 return (regs->trap); in kgdb_trap()
172 *ptr++ = regs->nip; in kgdb_getregs()
173 *ptr++ = regs->msr; in kgdb_getregs()
174 *ptr++ = regs->ccr; in kgdb_getregs()
176 *ptr++ = regs->ctr; in kgdb_getregs()
177 *ptr++ = regs->xer; in kgdb_getregs()
242 regs->nip = *ptr++; in kgdb_putregs()
[all …]
/u-boot/arch/riscv/lib/
A Dinterrupts.c34 regs->sp, regs->gp, regs->tp); in show_regs()
36 regs->t0, regs->t1, regs->t2); in show_regs()
38 regs->s0, regs->s1, regs->a0); in show_regs()
40 regs->a1, regs->a2, regs->a3); in show_regs()
42 regs->a4, regs->a5, regs->a6); in show_regs()
44 regs->a7, regs->s2, regs->s3); in show_regs()
46 regs->s4, regs->s5, regs->s6); in show_regs()
48 regs->s7, regs->s8, regs->s9); in show_regs()
50 regs->s10, regs->s11, regs->t3); in show_regs()
52 regs->t4, regs->t5, regs->t6); in show_regs()
[all …]
/u-boot/arch/arm/lib/
A Dinterrupts.c67 const int thumb = thumb_mode(regs); in dump_instr()
88 void show_regs (struct pt_regs *regs) in show_regs() argument
102 flags = condition_codes (regs); in show_regs()
105 instruction_pointer(regs), regs->ARM_lr); in show_regs()
112 regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); in show_regs()
114 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); in show_regs()
116 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); in show_regs()
118 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); in show_regs()
127 thumb_mode (regs) ? " (T)" : ""); in show_regs()
128 dump_instr(regs); in show_regs()
[all …]
/u-boot/drivers/video/
A Dbroadwell_igd.c28 u8 *regs; member
76 u8 *regs = priv->regs; in haswell_early_init() local
80 writel(0x00000020, regs + 0xa180); in haswell_early_init()
81 writel(0x00010001, regs + 0xa188); in haswell_early_init()
90 writel(0x00070020, regs + 0xa000); in haswell_early_init()
148 writel(0, regs + 0x138128); in haswell_early_init()
169 u8 *regs = priv->regs; in haswell_late_init() local
200 u8 *regs = priv->regs; in broadwell_early_init() local
275 writel(0, regs + 0x138128); in broadwell_early_init()
296 u8 *regs = priv->regs; in broadwell_late_init() local
[all …]
A Dmvebu_lcd.c98 uintptr_t regs; member
111 writel(0, regs + MVEBU_LCD_WIN_CONTROL(i)); in mvebu_lcd_conf_mbus_registers()
112 writel(0, regs + MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
113 writel(0, regs + MVEBU_LCD_WIN_REMAP(i)); in mvebu_lcd_conf_mbus_registers()
121 regs + MVEBU_LCD_WIN_CONTROL(i)); in mvebu_lcd_conf_mbus_registers()
129 uintptr_t regs) in mvebu_lcd_register_init() argument
137 mvebu_lcd_conf_mbus_registers(regs); in mvebu_lcd_register_init()
238 regs + MVEBU_LCD_SPU_H_PORCH); in mvebu_lcd_register_init()
248 regs + MVEBU_LCD_SPU_V_PORCH); in mvebu_lcd_register_init()
537 priv->regs = dev_read_addr(dev); in mvebu_video_probe()
[all …]
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_lradc_init.c23 writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr); in mxs_lradc_init()
24 writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr); in mxs_lradc_init()
27 clrsetbits_le32(&regs->hw_lradc_ctrl3, in mxs_lradc_init()
31 clrsetbits_le32(&regs->hw_lradc_ctrl4, in mxs_lradc_init()
55 clrsetbits_le32(&regs->hw_lradc_conversion, in mxs_lradc_enable_batt_measurement()
62 &regs->hw_lradc_ctrl2_clr); in mxs_lradc_enable_batt_measurement()
63 writel(0xffffffff, &regs->hw_lradc_ch7_clr); in mxs_lradc_enable_batt_measurement()
65 writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr); in mxs_lradc_enable_batt_measurement()
68 writel(1 << 7, &regs->hw_lradc_ctrl0_set); in mxs_lradc_enable_batt_measurement()
73 100, &regs->hw_lradc_delay3); in mxs_lradc_enable_batt_measurement()
[all …]
/u-boot/drivers/misc/
A Dmxc_ocotp.c204 wait_busy(*regs, 1); in prepare_access()
205 clear_error(*regs); in prepare_access()
215 clear_error(regs); in finish_access()
219 writel(1, &regs->pdn); in finish_access()
237 struct ocotp_regs *regs; in fuse_read() local
327 set_timing(regs); in setup_direct_access()
335 struct ocotp_regs *regs; in fuse_sense() local
349 wait_busy(regs, 1); in fuse_sense()
396 struct ocotp_regs *regs; in fuse_prog() local
407 writel(0, &regs->data1); in fuse_prog()
[all …]
/u-boot/arch/mips/mach-ath79/qca953x/
A Dddr.c223 void __iomem *regs; in ddr_init() local
234 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
308 regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
312 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
413 void __iomem *regs; in ddr_tap_tuning() local
419 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
426 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
427 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
444 val = readl(regs + DDR_REG_BIST_STATUS); in ddr_tap_tuning()
448 writel(0, regs + DDR_REG_BIST); in ddr_tap_tuning()
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