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/u-boot/drivers/reset/
A DMakefile6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
20 obj-$(CONFIG_RESET_MESON) += reset-meson.o
26 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
27 obj-$(CONFIG_RESET_QCOM) += reset-qcom.o
31 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
33 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
[all …]
A Dreset-at91.c40 if (!reset->dev_base) in at91_rst_update()
43 val = readl(reset->dev_base); in at91_rst_update()
48 writel(val, reset->dev_base); in at91_rst_update()
58 if (!reset->data->n_device_reset || in at91_reset_of_xlate()
59 args->args[0] < reset->data->device_reset_min_id || in at91_reset_of_xlate()
60 args->args[0] > reset->data->device_reset_max_id) in at91_reset_of_xlate()
72 return at91_rst_update(reset, reset_ctl->id, true); in at91_rst_assert()
79 return at91_rst_update(reset, reset_ctl->id, false); in at91_rst_deassert()
90 struct at91_reset *reset = dev_get_priv(dev); in at91_reset_probe() local
95 reset->dev_base = dev_remap_addr_index(dev, 1); in at91_reset_probe()
[all …]
A DKconfig4 bool "Enable reset controllers using Driver Model"
9 reset controller hardware module within the chip. In U-Boot, reset
16 bool "Enable the sandbox reset test driver"
24 bool "Enable the STi reset"
32 bool "Enable the STM32 reset"
39 bool "Enable Tegra CAR-based reset driver"
64 Support reset controller on BCM6345.
99 though is that some reset signals, like I2C or MISC reset multiple
173 U-Boot's reset framework to reset these hardware blocks.
206 initialization routines as reset lines.
[all …]
A Dreset-sunxi.c39 const struct ccu_reset *reset = plat_to_reset(plat, reset_ctl->id); in sunxi_set_reset() local
42 if (!(reset->flags & CCU_RST_F_IS_VALID)) { in sunxi_set_reset()
48 reset_ctl->id, reset->off, ilog2(reset->bit)); in sunxi_set_reset()
50 reg = readl(plat->base + reset->off); in sunxi_set_reset()
52 reg |= reset->bit; in sunxi_set_reset()
54 reg &= ~reset->bit; in sunxi_set_reset()
56 writel(reg, plat->base + reset->off); in sunxi_set_reset()
/u-boot/drivers/net/octeontx/
A Dxcv.c27 union xcvx_reset reset; in xcv_init_hw() local
32 reset.s.dllrst = 0; in xcv_init_hw()
37 reset.s.clkrst = 0; in xcv_init_hw()
52 reset.s.comp = 1; in xcv_init_hw()
63 reset.s.enable = 1; in xcv_init_hw()
68 reset.s.clkrst = 1; in xcv_init_hw()
80 union xcvx_reset reset; in xcv_setup_link() local
103 reset.s.tx_dat_rst_n = 1; in xcv_setup_link()
104 reset.s.rx_dat_rst_n = 1; in xcv_setup_link()
109 reset.s.tx_pkt_rst_n = 1; in xcv_setup_link()
[all …]
/u-boot/doc/device-tree-bindings/reset/
A Dreset.txt10 reset consumer (the module being reset, or a module managing when a sub-
14 A reset signal is represented by the phandle of the provider, plus a reset
24 may be reset. Instead, reset signals should be represented in the DT node
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
37 reset outputs.
41 rst: reset-controller {
42 #reset-cells = <1>;
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
63 reset-names = "reset";
[all …]
A Dsyscon-reset.txt1 Generic SYSCON mapped register reset driver
3 This is a generic reset driver using syscon to map the reset register.
4 The reset is generally performed with a write to the reset register
6 shifted by the reset specifier/
16 - compatible: should contain "syscon-reset"
17 - #reset-cells: must be 1
22 - mask: accept only the reset specifiers defined by the mask (32 bit)
23 - assert-high: Bit to write when asserting a reset. Defaults to 1.
29 reset-controller {
30 compatible = "syscon-reset";
[all …]
A Dti,sci-reset.txt13 The reset controller node represents the resets of various hardware modules
19 - compatible: Must be "ti,sci-reset"
20 - #reset-cells: Must be 2. Please see the reset consumer node below for
28 k3_reset: reset-controller {
29 compatible = "ti,sci-reset";
30 #reset-cells = <2>;
36 Each of the reset consumer nodes should have the following properties,
41 - resets: A phandle and reset specifier pair, one pair for each reset signal
43 should point to the TI SCI reset controller node, and the reset
45 the device ID. The second cell should contain the reset mask value
/u-boot/drivers/sysreset/
A DKconfig2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
20 Enable system reset drivers which can be used to reset the CPU or
29 Enable system reset drivers which can be used to reset the CPU or
39 Enable system reset drivers which can be used to reset the CPU or
70 bool "Enable support for GPIO reset driver"
75 pin which triggers cpu reset.
119 Enable system reset and poweroff via the SBI system reset extension.
[all …]
/u-boot/doc/device-tree-bindings/exynos/
A Demmc-reset.txt1 * Samsung eMMC reset
7 - compatible: should be "samsung,emmc-reset"
8 - reset-gpio: gpio chip for eMMC reset.
12 emmc-reset {
13 compatible = "samsung,emmc-reset";
14 reset-gpio = <&gpk1 2 0>;
/u-boot/arch/arm/dts/
A Dt8103-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
A Dast2600-u-boot.dtsi3 #include <dt-bindings/reset/ast2600-reset.h>
13 #reset-cells = <1>;
17 rst: reset-controller {
19 compatible = "aspeed,ast2600-reset";
21 #reset-cells = <1>;
30 #reset-cells = <1>;
A Dast2500-u-boot.dtsi3 #include <dt-bindings/reset/ast2500-reset.h>
13 #reset-cells = <1>;
16 rst: reset-controller {
18 compatible = "aspeed,ast2500-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
A Dimx6q-bx50v3-uboot.dtsi41 * with the kernel and the kernel should not reset the PHY, since
46 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
47 phy-reset-duration = <1>;
48 phy-reset-post-delay = <0>;
52 * PCIe reset is not done in the file shared with the kernel, since
55 * be reset by the kernel, so it may not reset PCIe via this GPIO.
58 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
A Dqcom-ipq4019.dtsi13 #include <dt-bindings/reset/qcom,ipq4019-reset.h>
58 #reset-cells = <1>;
69 reset: gcc-reset@1800000 { label
70 compatible = "qcom,gcc-reset-ipq4019";
73 #reset-cells = <1>;
139 resets = <&reset USB3_UNIPHY_PHY_ARES>;
140 reset-names = "por_rst";
149 resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
150 reset-names = "por_rst", "srif_rst";
182 resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
[all …]
/u-boot/doc/device-tree-bindings/gpu/
A Dnvidia,tegra20-host1x.txt15 See ../reset/reset.txt for details.
31 See ../reset/reset.txt for details.
44 See ../reset/reset.txt for details.
57 See ../reset/reset.txt for details.
70 See ../reset/reset.txt for details.
83 See ../reset/reset.txt for details.
100 See ../reset/reset.txt for details.
118 See ../reset/reset.txt for details.
149 See ../reset/reset.txt for details.
181 See ../reset/reset.txt for details.
[all …]
/u-boot/drivers/usb/host/
A Dxhci-pci.c19 struct reset_ctl reset; member
60 ret = reset_get_by_index(dev, 0, &plat->reset); in xhci_pci_probe()
66 if (reset_valid(&plat->reset)) { in xhci_pci_probe()
67 ret = reset_assert(&plat->reset); in xhci_pci_probe()
71 ret = reset_deassert(&plat->reset); in xhci_pci_probe()
87 if (reset_valid(&plat->reset)) in xhci_pci_probe()
88 reset_free(&plat->reset); in xhci_pci_probe()
98 if (reset_valid(&plat->reset)) in xhci_pci_remove()
99 reset_free(&plat->reset); in xhci_pci_remove()
A Dohci-npcm.c47 struct reset_ctl reset; in npcm_ohci_init() local
50 ret = reset_get_by_index(dev, 0, &reset); in npcm_ohci_init()
57 if (reset_valid(&reset)) in npcm_ohci_init()
58 reset_assert(&reset); in npcm_ohci_init()
66 if (reset_valid(&reset)) in npcm_ohci_init()
67 reset_deassert(&reset); in npcm_ohci_init()
/u-boot/arch/arm/mach-omap2/omap3/
A Demac.c20 u32 reset; in cpu_eth_init() local
23 reset = readl(&am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
24 reset &= ~CPGMACSS_SW_RST; in cpu_eth_init()
25 writel(reset, &am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
/u-boot/doc/usage/cmd/
A Dreset.rst3 reset command
11 reset [-w]
16 Perform reset of the CPU. By default does COLD reset, which resets CPU,
20 Do warm WARM, reset CPU but keep peripheral/DDR/PMIC active.
/u-boot/doc/device-tree-bindings/phy/
A Dphy-stih407-usb.txt9 - resets : list of phandle and reset specifier pairs. There should be two entries, one
11 - reset-names : list of reset signal names. Should be "global" and "port"
12 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
13 See: Documentation/devicetree/bindings/reset/reset.txt
23 reset-names = "global", "port";
/u-boot/arch/arm/mach-socfpga/
A Dreset_manager_s10.c21 void socfpga_per_reset(u32 reset, int set) in socfpga_per_reset() argument
25 if (RSTMGR_BANK(reset) == 0) in socfpga_per_reset()
27 else if (RSTMGR_BANK(reset) == 1) in socfpga_per_reset()
29 else if (RSTMGR_BANK(reset) == 2) in socfpga_per_reset()
31 else if (RSTMGR_BANK(reset) == 3) in socfpga_per_reset()
38 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
41 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/u-boot/doc/device-tree-bindings/i2c/
A Dgeneric-acpi.txt14 - reset-gpios : GPIO used to assert reset to the device
18 - reset-delay-ms : Delay after de-asserting reset, in ms
19 - reset-off-delay-ms : Delay after asserting reset (during power off)
37 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
38 reset-delay-ms = <20>;
/u-boot/drivers/mmc/
A Dmmc-pwrseq.c23 struct gpio_desc reset; in mmc_pwrseq_set_power() local
26 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); in mmc_pwrseq_set_power()
29 dm_gpio_set_value(&reset, 1); in mmc_pwrseq_set_power()
31 dm_gpio_set_value(&reset, 0); in mmc_pwrseq_set_power()
/u-boot/arch/x86/dts/
A Dreset.dtsi2 reset: reset { label
3 compatible = "x86,reset";

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