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Searched refs:sample (Results 1 – 25 of 112) sorted by relevance

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/u-boot/drivers/net/octeon/
A Docteon_mdio.c176 u32 sample; in octeon_mdio_probe() local
181 sample = (sclock + denom - 1) / denom; in octeon_mdio_probe()
182 debug("%s: sample: %u\n", __func__, smi_clk.s.sample); in octeon_mdio_probe()
183 if (sample < 2) { in octeon_mdio_probe()
186 sample = 2; in octeon_mdio_probe()
188 if (sample > (2 * smi_clk.s.phase - 3)) { in octeon_mdio_probe()
191 sample = 2 * smi_clk.s.phase - 3; in octeon_mdio_probe()
193 smi_clk.s.sample = sample & 0xf; in octeon_mdio_probe()
194 smi_clk.s.sample_hi = (sample >> 4) & 0xf; in octeon_mdio_probe()
196 dev->name, sample_dly, smi_clk.s.sample); in octeon_mdio_probe()
/u-boot/drivers/serial/
A Dserial_cortina.c68 unsigned int uart_ctrl, baud, sample; in ca_serial_setbrg() local
77 sample = baud / 2; in ca_serial_setbrg()
78 sample = (sample < 7) ? 7 : sample; in ca_serial_setbrg()
79 writel(sample, priv->base + URX_SAMPLE); in ca_serial_setbrg()
/u-boot/board/bosch/shc/
A DKconfig52 activate, if you want to build for the B sample version
58 activate, if you want to build for the B2 sample version
64 activate, if you want to build for the C sample version
70 activate, if you want to build for the C2 sample version
76 activate, if you want to build for the C3 sample version
/u-boot/doc/device-tree-bindings/exynos/
A Dsound.txt10 - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
22 samsung,i2s-bits-per-sample = <16>;
A Ddwmmc.txt30 Drv/sample clock selection register of corresponding channel.
33 . SelClk_sample: Select sample clock among 8 shifted clocks.
/u-boot/arch/arm/dts/
A Darmada-ap806.dtsi21 compatible = "marvell,sample-at-reset-common",
22 "marvell,sample-at-reset-ap806";
A Darmada-ap807.dtsi21 compatible = "marvell,sample-at-reset-common",
22 "marvell,sample-at-reset-ap807";
A Dexynos5250.dtsi89 samsung,i2s-bits-per-sample = <16>;
103 samsung,i2s-bits-per-sample = <16>;
A Drv1126-edgeble-neu2-io.dts32 rockchip,default-sample-phase = <90>;
A Dstm32mp157c-odyssey.dts50 st,min-sample-time-nsecs = <5000>;
58 st,min-sample-time-nsecs = <5000>;
A Dstm32mp15xx-dhcor-testbench.dts52 st,min-sample-time-nsecs = <5000>;
58 st,min-sample-time-nsecs = <5000>;
A Dcn9130-db-dev-info.dtsi13 compatible = "marvell,sample-at-reset";
A Dsocfpga_cyclone5_mcvevk.dts62 ts,sample-time = <4>;
A Dstm32f429-disco.dts87 st,sample-time = <4>;
91 /* 8 sample average control */
A Dsun8i-s3-pinecube.dts73 pclk-sample = <1>; /* Rising */
120 pclk-sample = <1>; /* Rising */
A Dsun8i-h3.dtsi298 "sample";
310 "sample";
322 "sample";
/u-boot/drivers/rng/
A Dsmccc_trng.c61 u32 sample = *rnd; in smc32_copy_sample() local
63 memcpy(*ptr, &sample, len); in smc32_copy_sample()
72 u64 sample = *rnd; in smc64_copy_sample() local
74 memcpy(*ptr, &sample, len); in smc64_copy_sample()
/u-boot/drivers/rtc/
A Darmada38x.c68 u32 sample = readl(rtc->regs + reg); in armada38x_rtc_read() local
72 if (samples[j] == sample) in armada38x_rtc_read()
81 samples[last] = sample; in armada38x_rtc_read()
/u-boot/arch/x86/cpu/quark/
A Dmrc_util.c1095 uint8_t sample; /* sample counter */ in find_rising_edge() local
1110 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1116 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1119 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1124 sample_result[sample] = sample_dqs(mrc_params, in find_rising_edge()
1129 rcvn ? "RCVN" : "WDQS", channel, rank, sample, in find_rising_edge()
1130 sample * SAMPLE_DLY, sample_result[sample]); in find_rising_edge()
1140 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1142 ((sample_result[sample] & (1 << bl)) >> bl) << in find_rising_edge()
1143 (SAMPLE_CNT - 1 - sample); in find_rising_edge()
/u-boot/drivers/adc/
A DKconfig21 - 600 KSPS of sample rate
40 - Up to 1MSPS of sample rate
49 - Up to 1MSPS of sample rate
/u-boot/doc/device-tree-bindings/video/
A Ddisplay-timing.txt31 sample data on falling edge
33 sample data on rising edge
/u-boot/doc/board/intel/
A Dbayleybay.rst16 from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
/u-boot/arch/mips/mach-octeon/include/mach/
A Dcvmx-smix-defs.h145 u64 sample : 4; member
155 u64 sample : 4; member
/u-boot/board/Marvell/dreamplug/
A Dkwbimage.cfg38 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
110 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz

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