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Searched refs:sclk (Results 1 – 25 of 34) sorted by relevance

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/u-boot/drivers/clk/
A Dclk-hsdk-cgu.c564 ulong parent_rate = pll_get(sclk); in idiv_get()
582 ret = pll_set(sclk, rate); in cpu_clk_set()
583 idiv_set(sclk, rate); in cpu_clk_set()
601 pll_rate = pll_get(sclk); in common_div_clk_set()
654 ulong parent_rate = pll_get(sclk); in idiv_set()
686 if (sclk->id >= CGU_MAX_CLOCKS) in hsdk_prepare_clock_tree_branch()
708 return clk->map[sclk->id].get_rate(sclk); in hsdk_cgu_get_rate()
718 if (clk->map[sclk->id].set_rate) in hsdk_cgu_set_rate()
719 return clk->map[sclk->id].set_rate(sclk, rate); in hsdk_cgu_set_rate()
731 if (clk->map[sclk->id].disable) in hsdk_cgu_disable()
[all …]
/u-boot/arch/arm/mach-exynos/
A Dclock.c369 unsigned long sclk = 0; in exynos5_get_periph_rate() local
468 unsigned long sclk = 0; in exynos542x_get_periph_rate() local
641 unsigned long pclk, sclk; in exynos4_get_pwm_clk() local
682 unsigned long pclk, sclk; in exynos4x12_get_pwm_clk() local
685 sclk = get_pll_clk(MPLL); in exynos4x12_get_pwm_clk()
698 unsigned long uclk, sclk; in exynos4_get_uart_clk() local
745 unsigned long uclk, sclk; in exynos4x12_get_uart_clk() local
789 unsigned long uclk, sclk; in exynos4_get_mmc_clk() local
918 unsigned long pclk, sclk; in exynos4_get_lcd_clk() local
960 unsigned long pclk, sclk; in exynos5_get_lcd_clk() local
[all …]
/u-boot/board/freescale/common/
A Dngpixis.c142 PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); in pixis_dump_regs()
169 PIXIS_WRITE(sclk[0], sclk0); in pixis_sysclk_set()
170 PIXIS_WRITE(sclk[1], sclk1); in pixis_sysclk_set()
171 PIXIS_WRITE(sclk[2], sclk2); in pixis_sysclk_set()
A Dics307_clk.c136 in_8(&fpga_reg->sclk[0]), in get_board_sys_clk()
137 in_8(&fpga_reg->sclk[1]), in get_board_sys_clk()
138 in_8(&fpga_reg->sclk[2])); in get_board_sys_clk()
A Dqixis.c215 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), in qixis_dump_regs()
216 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); in qixis_dump_regs()
A Dngpixis.h38 u8 sclk[3]; member
A Dqixis.h52 u8 sclk[3]; /* Clock Configuration Registers,0x34 */ member
/u-boot/drivers/mmc/
A Dexynos_dw_mmc.c63 unsigned long sclk; in exynos_dwmci_get_clk() local
74 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_get_clk()
80 return sclk / clk_div / (host->div + 1); in exynos_dwmci_get_clk()
105 unsigned long freq, sclk; in exynos_dwmci_core_init() local
113 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_core_init()
114 div = DIV_ROUND_UP(sclk, freq); in exynos_dwmci_core_init()
A Dftsdc010_mci.h17 uint32_t sclk; /* FTSDC010 source clock in Hz */ member
A Dmtk-sd.c370 u32 sclk; /* actual calculated bus clock */ member
803 if (host->sclk == 0) { in msdc_set_timeout()
806 clk_ns = 1000000000UL / host->sclk; in msdc_set_timeout()
853 u32 sclk; in msdc_set_mclk() local
877 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
881 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
893 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
899 sclk = host->src_clk_freq; in msdc_set_mclk()
908 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
933 host->sclk = sclk; in msdc_set_mclk()
[all …]
A Ddw_mmc.c406 unsigned long sclk; local
416 sclk = host->get_mmc_clk(host, freq);
418 sclk = host->bus_hz;
424 if (sclk == freq)
427 div = DIV_ROUND_UP(sclk, 2 * freq);
A Dftsdc010_mci.c141 if (rate >= chip->sclk / (2 * (div + 1))) in ftsdc010_clkset()
144 chip->rate = chip->sclk / (2 * (div + 1)); in ftsdc010_clkset()
413 chip->sclk = priv->minmax[1]; in ftsdc010_mmc_of_to_plat()
/u-boot/drivers/reset/
A Dreset-at91.c91 struct clk sclk; in at91_reset_probe() local
99 ret = clk_get_by_index(dev, 0, &sclk); in at91_reset_probe()
103 return clk_prepare_enable(&sclk); in at91_reset_probe()
/u-boot/arch/arm/dts/
A Dmeson-g12.dtsi21 clock-names = "mclk", "sclk", "lrclk";
32 clock-names = "mclk", "sclk", "lrclk";
43 clock-names = "mclk", "sclk", "lrclk";
208 clock-names = "pclk", "sclk", "sclk_sel",
224 clock-names = "pclk", "sclk", "sclk_sel",
240 clock-names = "pclk", "sclk", "sclk_sel",
256 clock-names = "pclk", "sclk", "sclk_sel",
298 clock-names = "pclk", "sclk", "sclk_sel",
313 clock-names = "pclk", "sclk", "sclk_sel",
328 clock-names = "pclk", "sclk", "sclk_sel",
A Dmeson-sm1.dtsi23 clock-names = "mclk", "sclk", "lrclk";
34 clock-names = "mclk", "sclk", "lrclk";
45 clock-names = "mclk", "sclk", "lrclk";
287 clock-names = "pclk", "sclk", "sclk_sel",
303 clock-names = "pclk", "sclk", "sclk_sel",
319 clock-names = "pclk", "sclk", "sclk_sel",
335 clock-names = "pclk", "sclk", "sclk_sel",
377 clock-names = "pclk", "sclk", "sclk_sel",
392 clock-names = "pclk", "sclk", "sclk_sel",
407 clock-names = "pclk", "sclk", "sclk_sel",
A Dmeson-axg.dtsi31 clock-names = "mclk", "sclk", "lrclk";
42 clock-names = "mclk", "sclk", "lrclk";
53 clock-names = "mclk", "sclk", "lrclk";
1416 clock-names = "pclk", "sclk", "sclk_sel",
1430 clock-names = "pclk", "sclk", "sclk_sel",
1444 clock-names = "pclk", "sclk", "sclk_sel",
1458 clock-names = "pclk", "sclk", "sclk_sel",
1495 clock-names = "pclk", "sclk", "sclk_sel",
1509 clock-names = "pclk", "sclk", "sclk_sel",
1523 clock-names = "pclk", "sclk", "sclk_sel",
A Dmeson-g12-common.dtsi1107 tdm_a_sclk_pins: tdm-a-sclk {
1125 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1227 tdm_b_sclk_pins: tdm-b-sclk {
1244 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1445 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1454 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1479 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1487 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1869 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1886 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
A Dfsl-ls1028a-rdb.dts205 sclk-strength = <3>;
A Dstih407-pinctrl.dtsi1097 sclk = <&pio33 6 ALT1 OUT>;
1109 sclk = <&pio33 6 ALT1 OUT>;
1120 sclk = <&pio32 6 ALT1 IN>;
1133 sclk = <&pio32 6 ALT1 IN>;
/u-boot/drivers/spi/
A Dsoft_spi.c28 struct gpio_desc sclk; member
47 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
70 dm_gpio_set_value(&plat->sclk, cidle); /* to idle */ in soft_spi_cs_activate()
253 gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, in soft_spi_probe()
/u-boot/drivers/i2c/
A Docteon_i2c.c610 static void twsi_calc_div(struct udevice *bus, ulong sclk, unsigned int speed, in twsi_calc_div() argument
619 tclk = sclk / (2 * (thp + 1)); in twsi_calc_div()
622 sclk = 100000000; /* 100 Mhz */ in twsi_calc_div()
623 tclk = sclk / (thp + 2); in twsi_calc_div()
625 debug("%s( io_clock %lu tclk %u)\n", __func__, sclk, tclk); in twsi_calc_div()
/u-boot/doc/device-tree-bindings/i2c/
A Docteon-i2c.txt23 clocks = <&sclk>;
/u-boot/drivers/mtd/nand/raw/
A Docteontx_nand.c563 unsigned long sclk) in set_timings() argument
569 s_wh = timing_to_cycle(timings->tWH_min, sclk); in set_timings()
570 s_cls = timing_to_cycle(timings->tCLS_min, sclk); in set_timings()
571 s_clh = timing_to_cycle(timings->tCLH_min, sclk); in set_timings()
572 s_rp = timing_to_cycle(timings->tRP_min, sclk); in set_timings()
573 s_wb = timing_to_cycle(timings->tWB_max, sclk); in set_timings()
574 s_wc = timing_to_cycle(timings->tWC_min, sclk); in set_timings()
596 unsigned long sclk = octeontx_get_io_clock(); in set_default_timings() local
598 set_timings(NULL, &default_timing_parms, timings, sclk); in set_default_timings()
606 unsigned long sclk = octeontx_get_io_clock(); in octeontx_nfc_chip_set_timings() local
[all …]
/u-boot/doc/device-tree-bindings/clock/
A Dnvidia,tegra20-car.txt138 107 sclk
/u-boot/doc/device-tree-bindings/video/
A Dexynos-fb.txt56 samsung,sclk-div: parent_clock/source_clock ratio

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