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Searched refs:sdelay (Results 1 – 25 of 35) sorted by relevance

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/u-boot/arch/arm/mach-exynos/
A Ddmc_init_exynos4.c95 sdelay(0x100000); in dmc_init()
140 sdelay(0x100000); in dmc_init()
144 sdelay(0x100000); in dmc_init()
148 sdelay(0x100000); in dmc_init()
151 sdelay(0x100000); in dmc_init()
155 sdelay(0x100000); in dmc_init()
159 sdelay(0x100000); in dmc_init()
162 sdelay(0x100000); in dmc_init()
A Ddmc_common.c56 sdelay(100); in dmc_config_zq()
65 sdelay(100); in dmc_config_zq()
116 sdelay(0x10000); in dmc_config_mrs()
122 sdelay(0x10000); in dmc_config_mrs()
130 sdelay(10000); in dmc_config_mrs()
149 sdelay(0x10000); in dmc_config_prech()
A Dclock_init_exynos4.c46 sdelay(0x10000); in system_clock_init()
60 sdelay(0x10000); in system_clock_init()
93 sdelay(0x30000); in system_clock_init()
A Dcommon_setup.h47 void sdelay(unsigned long);
A Ddmc_init_ddr3.c191 sdelay(100); in ddr3_mem_ctrl_init()
646 sdelay(10); in ddr3_mem_ctrl_init()
656 sdelay(10); in ddr3_mem_ctrl_init()
752 sdelay(100); in ddr3_mem_ctrl_init()
767 sdelay(100); in ddr3_mem_ctrl_init()
/u-boot/arch/arm/mach-sunxi/
A Dclock_sun9i.c105 sdelay(2000); in clock_set_pll1()
126 sdelay(2000); in clock_set_pll2()
144 sdelay(2000); in clock_set_pll6()
158 sdelay(2000); in clock_set_pll12()
170 sdelay(2000); in clock_set_pll4()
A Dclock_sun4i.c30 sdelay(200); in clock_init_safe()
158 sdelay(20); in clock_set_pll1()
169 sdelay(200); in clock_set_pll1()
177 sdelay(20); in clock_set_pll1()
A Dclock_sun8i_a83t.c33 sdelay(50); in clock_init_safe()
35 sdelay(100); in clock_init_safe()
A Ddram_sun9i.c279 sdelay(2000); in mctl_sys_init()
289 sdelay(1000); in mctl_sys_init()
297 sdelay(10000); in mctl_sys_init()
305 sdelay(2000); in mctl_sys_init()
333 sdelay(1000); in mctl_sys_init()
756 sdelay(10000); /* XXX necessary? */ in mctl_channel_init()
762 sdelay(1000); in mctl_channel_init()
805 sdelay(100000); in mctl_channel_init()
/u-boot/arch/arm/mach-keystone/
A Dclock.c46 sdelay(450); in wait_for_completion()
58 sdelay(340); in bypass_main_pll()
99 sdelay(210000); in configure_main_pll()
114 sdelay(21000); in configure_main_pll()
153 sdelay(21000); /* Wait for a minimum of 7 us*/ in configure_main_pll()
155 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ in configure_main_pll()
186 sdelay(21000); in configure_secondary_pll()
194 sdelay(105000); in configure_secondary_pll()
216 sdelay(210000); in init_pll()
/u-boot/arch/arm/mach-omap2/omap3/
A Dspl_id_nand.c35 sdelay(2000); in identify_nand_chip()
42 sdelay(100); in identify_nand_chip()
A Dsdrc.c169 sdelay(0x20000); in do_sdrc_init()
/u-boot/arch/arm/mach-omap2/
A Dmem-common.c71 sdelay(1000); in enable_gpmc_cs_config()
82 sdelay(2000); in enable_gpmc_cs_config()
152 sdelay(1000); in set_gpmc_cs0()
A Dvc.c124 sdelay(100); in omap_vc_bypass_send_value()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dsys_proto.h13 void sdelay(unsigned long);
/u-boot/arch/arm/cpu/arm926ejs/
A Dcpu.c31 void sdelay(unsigned long loops) in sdelay() function
/u-boot/arch/arm/cpu/armv7/
A Dsyslib.c20 void sdelay(unsigned long loops) in sdelay() function
/u-boot/arch/arm/cpu/armv8/
A Dcpu.c30 void sdelay(unsigned long loops) in sdelay() function
/u-boot/drivers/adc/
A Dadc-uclass.c26 #define sdelay(x) udelay(x) macro
28 extern void sdelay(unsigned long loops);
164 sdelay(5); in adc_channel_data()
191 sdelay(5); in adc_channels_data()
/u-boot/arch/arm/include/asm/arch-am33xx/
A Dsys_proto.h26 void sdelay(unsigned long);
/u-boot/arch/arm/include/asm/arch-omap4/
A Dsys_proto.h48 void sdelay(unsigned long);
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_arria10.c18 void sdelay(unsigned long loops);
558 sdelay(1000000); /* 1ms */ in cm_pll_ramp_main()
564 sdelay(1000000); /* 1ms */ in cm_pll_ramp_main()
592 sdelay(1000000); /* 1ms */ in cm_pll_ramp_periph()
598 sdelay(1000000); /* 1ms */ in cm_pll_ramp_periph()
743 sdelay(5000); in cm_full_cfg()
754 sdelay(7000); in cm_full_cfg()
/u-boot/arch/arm/include/asm/arch-omap3/
A Dsys_proto.h59 void sdelay(unsigned long);
/u-boot/arch/arm/include/asm/arch-omap5/
A Dsys_proto.h53 void sdelay(unsigned long);
/u-boot/drivers/ram/
A Dk3-am654-ddrss.c20 void sdelay(unsigned long loops);
189 sdelay(10); /* Delay at least 20 clock cycles */ \
195 sdelay(10); /* Delay at least 20 clock cycles */ \
328 sdelay(5); /* Delay at least 10 clock cycles */ in __phy_builtin_init_routine()
334 sdelay(16); /* Delay at least 32 clock cycles */ in __phy_builtin_init_routine()
519 sdelay(16); in enable_dqs_pd()
539 sdelay(16); in disable_dqs_pd()

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