Searched refs:sdiv (Results 1 – 8 of 8) sorted by relevance
| /u-boot/drivers/clk/exynos/ |
| A D | clk-pll.c | 22 unsigned long mdiv, sdiv, pdiv; in pll145x_get_rate() local
27 sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; in pll145x_get_rate()
30 do_div(fvco, (pdiv << sdiv)); in pll145x_get_rate()
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| /u-boot/drivers/clk/imx/ |
| A D | clk-pll14xx.c | 60 .sdiv = (_s), \
68 .sdiv = (_s), \
133 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
138 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
141 do_div(fvco, pdiv << sdiv); in clk_pll1416x_recalc_rate()
157 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
164 do_div(fvco, pdiv << sdiv); in clk_pll1443x_recalc_rate()
232 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
253 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
299 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
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| A D | clk.h | 34 unsigned int sdiv; member
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| /u-boot/arch/arm/mach-exynos/ |
| A D | exynos4_setup.h | 327 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
330 | (sdiv << 0))
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| A D | exynos5_setup.h | 22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) argument
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | clock_imx8mm.h | 20 .sdiv = (_s), \
42 int sdiv; member
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| /u-boot/board/samsung/trats/ |
| A D | setup.h | 229 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
232 | (sdiv << 0))
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| /u-boot/arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mm.c | 113 (rate->sdiv << SDIV_SHIFT); in fracpll_configure()
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