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/u-boot/arch/arm/dts/
A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
98 cache-sets = <512>;
107 cache-sets = <512>;
A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
88 i-cache-sets = <256>;
91 d-cache-sets = <128>;
101 cache-sets = <512>;
A Dk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
88 i-cache-sets = <256>;
91 d-cache-sets = <128>;
101 cache-sets = <512>;
A Dk3-am642.dtsi36 i-cache-sets = <256>;
39 d-cache-sets = <128>;
50 i-cache-sets = <256>;
53 d-cache-sets = <128>;
63 cache-sets = <256>;
A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
200 cache-sets = <2048>;
[all …]
A Dsynquacer-sc2a11-caches.dtsi11 i-cache-sets = <256>; \
14 d-cache-sets = <128>; \
22 cache-sets = <256>; \
45 cache-sets = <4096>;
A Dk3-j7200.dtsi60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
87 cache-sets = <2048>;
A Dk3-j721s2.dtsi48 i-cache-sets = <256>;
51 d-cache-sets = <256>;
62 i-cache-sets = <256>;
65 d-cache-sets = <256>;
75 cache-sets = <1024>;
A Dk3-j721e.dtsi61 i-cache-sets = <256>;
64 d-cache-sets = <128>;
75 i-cache-sets = <256>;
78 d-cache-sets = <128>;
88 cache-sets = <2048>;
A Drk3588s.dtsi66 i-cache-sets = <128>;
69 d-cache-sets = <128>;
85 i-cache-sets = <128>;
88 d-cache-sets = <128>;
104 i-cache-sets = <128>;
107 d-cache-sets = <128>;
123 i-cache-sets = <128>;
224 cache-sets = <512>;
232 cache-sets = <512>;
240 cache-sets = <512>;
[all …]
/u-boot/arch/riscv/dts/
A Dfu540-c000.dtsi29 i-cache-sets = <128>;
43 d-cache-sets = <64>;
45 d-tlb-sets = <1>;
49 i-cache-sets = <64>;
51 i-tlb-sets = <1>;
69 d-tlb-sets = <1>;
75 i-tlb-sets = <1>;
93 d-tlb-sets = <1>;
99 i-tlb-sets = <1>;
117 d-tlb-sets = <1>;
[all …]
A Dfu740-c000.dtsi29 i-cache-sets = <128>;
44 d-cache-sets = <64>;
46 d-tlb-sets = <1>;
52 i-tlb-sets = <1>;
68 d-cache-sets = <64>;
70 d-tlb-sets = <1>;
76 i-tlb-sets = <1>;
94 d-tlb-sets = <1>;
100 i-tlb-sets = <1>;
118 d-tlb-sets = <1>;
[all …]
A Dmicrochip-mpfs.dtsi25 i-cache-sets = <128>;
47 d-cache-sets = <64>;
49 d-tlb-sets = <1>;
53 i-cache-sets = <64>;
55 i-tlb-sets = <1>;
81 d-tlb-sets = <1>;
87 i-tlb-sets = <1>;
113 d-tlb-sets = <1>;
119 i-tlb-sets = <1>;
145 d-tlb-sets = <1>;
[all …]
A Djh7110.dtsi24 i-cache-sets = <64>;
41 d-cache-sets = <64>;
43 d-tlb-sets = <1>;
47 i-cache-sets = <64>;
49 i-tlb-sets = <1>;
69 d-tlb-sets = <1>;
75 i-tlb-sets = <1>;
95 d-tlb-sets = <1>;
101 i-tlb-sets = <1>;
121 d-tlb-sets = <1>;
[all …]
/u-boot/doc/usage/cmd/
A Dpart.rst24 The 'part uuid' command prints or sets an environment variable to partition UUID
35 The 'part list' command prints or sets an environment variable to the list of partitions
49 The 'part start' commnad sets an environment variable to the start of the partition (in blocks),
61 The 'part size' command sets an environment variable to the size of the partition (in blocks),
73 The 'part number' command sets an environment variable to the partition number using the partition …
85 The 'part type' command prints or sets an environment variable to the partition type UUID.
A Dfalse.rst14 The false command sets the return value $? to 1 (false).
A Dtrue.rst14 The true command sets the return value $? to 0 (true).
A Dbase.rst16 The *base* command sets or displays the address offset used by the memory
A Dsize.rst16 The size command determines the size of a file and sets the environment variable
/u-boot/arch/arm/cpu/armv7m/
A Dcache.c64 u32 sets; member
72 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT; in get_cache_ways_sets()
189 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
190 for (i = cache.sets; i >= 0; i--) { in action_dcache_all()
/u-boot/doc/board/google/
A Dchromebook_link.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
12 * video ROM - sets up the display
A Dchromebook_samus.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
13 * vga.bin - video ROM, which sets up the display
/u-boot/doc/device-tree-bindings/gpio/
A Dintel,x86-broadwell-pinctrl.txt14 - output-value - sets the default output value of the GPIO, 0 (low, default)
16 - direction - sets the direction of the gpio, either PIN_INPUT (default)
19 - trigger - sets the trigger type, either TRIGGER_EDGE (default) or
22 - owner 0 sets the owner of the pin, either OWNER_ACPI (default) or
24 - route - sets whether the pin is routed, either PIRQ_APIC_MASK or
/u-boot/board/boundary/nitrogen6x/
A Dclocks.cfg38 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
/u-boot/doc/arch/sandbox/
A Dblock_impl.rst19 Devices are created using `host_create_device()`. This sets up a new

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