| /u-boot/test/common/ |
| A D | event.c | 26 test_state->val += data->signal; in h_adder()
34 int signal; in test_event_base() local
39 signal = 17; in test_event_base()
42 ut_assertok(event_notify(EVT_TEST, &signal, sizeof(signal))); in test_event_base()
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| /u-boot/doc/device-tree-bindings/reset/ |
| A D | reset.txt | 8 Hardware blocks typically receive a reset signal. This signal is generated by
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
22 at once. In this case, it would be unwise to represent this reset signal in
26 children of the bus are affected by the reset signal, or an individual HW
29 rather than to slavishly enumerate the reset signal that affects each HW
49 for each reset signal that affects the device, or that the
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
66 This represents a device with a single reset signal named "reset".
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| /u-boot/doc/device-tree-bindings/serial/ |
| A D | snps-dw-apb-uart.txt | 27 - dcd-override : Override the DCD modem status signal. This signal will always
30 - dsr-override : Override the DTS modem status signal. This signal will always
33 - cts-override : Override the CTS modem status signal. This signal will always
36 - ri-override : Override the RI modem status signal. This signal will always be
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| /u-boot/test/py/ |
| A D | u_boot_spawn.py | 11 import signal
57 signal.signal(signal.SIGHUP, signal.SIG_DFL)
111 self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum).name)
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| /u-boot/test/py/tests/ |
| A D | test_sandbox_exit.py | 6 import signal
20 u_boot_console.kill(signal.SIGINT)
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| A D | test_stackprotector.py | 5 import signal
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| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | fsl,mpc83xx-spisel-boot.txt | 3 Provide access to MPC83xx SPISEL_BOOT signal as a gpio to allow it to be
6 The SPISEL_BOOT signal is always an output.
|
| A D | gpio.txt | 93 defined by the binding for the device. If the board inverts the signal between
95 opposite physical level than the signal at the device's pin.
97 When the device's signal polarity is configurable, the binding for the
100 a) Define a single static polarity for the signal, with the expectation that
102 that signal polarity.
114 concepts of configurable signal polarity in the device, and possible board-
115 level signal inversion.
119 b) Pick a single option for device signal polarity, and document this choice
120 in the binding. The gpio-specifier should represent the polarity of the signal
122 particular signal polarity choice. If software chooses to program the device
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| /u-boot/board/buffalo/lsxl/ |
| A D | kwbimage-lschl.cfg | 139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| A D | kwbimage-lsxhl.cfg | 139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| /u-boot/arch/arm/dts/ |
| A D | meson-sm1-odroid-c4.dts | 33 * WARNING: The USB Hub on the Odroid-C4 needs a reset signal
35 * This signal should be handled by a USB specific power sequence
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| A D | px30-ringneck-haikou-u-boot.dtsi | 50 * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
51 * eMMC powered-down initially (in fact it keeps the reset signal
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| A D | rk3399-puma-haikou-u-boot.dtsi | 72 * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
74 * reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable
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| A D | meson-gxbb-odroidc2.dts | 41 * signal name from schematics: PWREN
46 * signal name from schematics: USB_POWER
87 * signal name from schematics: TFLASH_VDD_EN
103 * signal name from schematics: TF_3V3N_1V8_EN
255 * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
257 * This signal should be handled by a USB specific power sequence
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| A D | stm32mp15xx-dhcom-picoitx.dtsi | 45 * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
46 * port power. This signal should be handled by USB power sequencing
|
| A D | imx8mp-verdin-dev.dtsi | 43 /* Limit frequency on dev board due to long traces and bad signal integrity */
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| /u-boot/arch/powerpc/include/asm/ |
| A D | sigcontext.h | 9 int signal; member
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| /u-boot/board/d-link/dns325/ |
| A D | kwbimage.cfg | 128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| /u-boot/doc/usage/cmd/ |
| A D | gpio.rst | 25 Switch the GPIO *pin* to output mode and set the signal to 1.
30 Switch the GPIO *pin* to output mode and set the signal to 0.
35 Switch the GPIO *pin* to output mode and reverse the signal state.
40 Read the signal state of the GPIO *pin* and save it in environment variable
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| /u-boot/doc/device-tree-bindings/thermal/ |
| A D | ti_soc_thermal.txt | 15 the talert signal is routed to;
22 line the tshut signal is routed to. The informed GPIO will
|
| /u-boot/doc/device-tree-bindings/spi/ |
| A D | spi-mcf-dspi.txt | 17 select and the start of clock signal, at the start of a transfer.
19 signal and deactivating chip select, at the end of a transfer.
|
| /u-boot/doc/device-tree-bindings/net/ |
| A D | snps,dwc-qos-ethernet.txt | 25 The EQOS transmit path clock. The HW signal name is clk_tx_i.
30 The EQOS receive path clock. The HW signal name is clk_rx_i.
41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
45 separate clock for the master and slave bus interfaces. The HW signal name
48 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
85 - interrupts: Should contain the core's combined interrupt signal
91 - "eqos". The reset to the entire module. The HW signal name is hreset_n
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| /u-boot/doc/device-tree-bindings/memory/ |
| A D | ti,gpmc-child.yaml | 28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
41 # ADV signal timings corresponding to GPMC_CONFIG3:
129 description: ADV signal is delayed by half GPMC clock
133 description: CS signal is delayed by half GPMC clock
149 description: OE signal is delayed by half GPMC clock
153 description: WE signal is delayed by half GPMC clock
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| /u-boot/doc/imx/common/ |
| A D | imx5.txt | 20 This option should be enabled for boards having a SYS_ON_OFF_CTL signal
21 connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
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| /u-boot/include/ |
| A D | event.h | 50 int signal; member
|