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/u-boot/arch/nios2/lib/
A Dcache.c19 start &= ~(gd->arch.dcache_line_size - 1); in __flush_dcache()
39 if (end > start + gd->arch.dcache_size) in __flush_dcache_all()
40 end = start + gd->arch.dcache_size; in __flush_dcache_all()
75 end = start + gd->arch.icache_size; in __flush_icache()
95 __flush_dcache(start, end); in flush_dcache_range()
97 __flush_dcache_all(start, end); in flush_dcache_range()
103 __flush_dcache(start, start + size); in flush_cache()
105 __flush_dcache_all(start, start + size); in flush_cache()
106 __flush_icache(start, start + size); in flush_cache()
112 __invalidate_dcache(start, end); in invalidate_dcache_range()
[all …]
/u-boot/arch/arm/cpu/armv7/
A Dcache_v7.c37 start &= ~(line_len - 1); in v7_dcache_clean_inval_range()
38 for (mva = start; mva < stop; mva = mva + line_len) { in v7_dcache_clean_inval_range()
48 if (!check_cache_range(start, stop)) in v7_dcache_inval_range()
51 for (mva = start; mva < stop; mva = mva + line_len) { in v7_dcache_inval_range()
71 v7_dcache_clean_inval_range(start, stop, line_len); in v7_dcache_maint_range()
74 v7_dcache_inval_range(start, stop, line_len); in v7_dcache_maint_range()
121 check_cache_range(start, stop); in invalidate_dcache_range()
125 v7_outer_cache_inval_range(start, stop); in invalidate_dcache_range()
135 check_cache_range(start, stop); in flush_dcache_range()
139 v7_outer_cache_flush_range(start, stop); in flush_dcache_range()
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A Dvirt-dt.c29 int armv7_apply_memory_carveout(u64 *start, u64 *size) in armv7_apply_memory_carveout() argument
32 if (*start + *size < CONFIG_ARMV7_SECURE_BASE || in armv7_apply_memory_carveout()
33 *start >= (u64)CONFIG_ARMV7_SECURE_BASE + in armv7_apply_memory_carveout()
38 if (*start == CONFIG_ARMV7_SECURE_BASE || in armv7_apply_memory_carveout()
39 *start + *size == (u64)CONFIG_ARMV7_SECURE_BASE + in armv7_apply_memory_carveout()
46 if (*start == CONFIG_ARMV7_SECURE_BASE) in armv7_apply_memory_carveout()
47 *start += CONFIG_ARMV7_SECURE_RESERVE_SIZE; in armv7_apply_memory_carveout()
/u-boot/fs/btrfs/
A Dextent-cache.c30 if (entry->start + entry->size <= range->start) in cache_tree_comp_range()
44 range.start = entry->start; in cache_tree_comp_nodes()
77 range.start = entry->start; in cache_tree_comp_nodes2()
96 pe->start = start; in alloc_cache_extent()
133 range.start = start; in lookup_cache_extent()
151 range.start = start; in lookup_cache_extent2()
168 range.start = start; in search_cache_extent()
189 range.start = start; in search_cache_extent2()
283 } else if (start <= cache->start) { in add_merge_cache_extent()
301 next->start = start; in add_merge_cache_extent()
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A Dextent-io.c87 state->start = other->start; in merge_state()
99 other->start = state->start; in merge_state()
120 state->start = start; in insert_state()
138 prealloc->start = orig->start; in split_state()
269 if (state->start < start) { in clear_extent_bits()
281 start = state->start; in clear_extent_bits()
381 if (state->start < start) { in set_extent_bits()
395 start = state->start; in set_extent_bits()
406 if (state->start > start) { in set_extent_bits()
534 if (state->start != start) { in set_state_private()
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A Dextent-io.h54 #define BITMAP_FIRST_BYTE_MASK(start) \ argument
55 ((BYTE_MASK << ((start) & (BITS_PER_BYTE - 1))) & BYTE_MASK)
74 u64 start; member
83 u64 start; member
100 int find_first_extent_bit(struct extent_io_tree *tree, u64 start,
102 int test_range_bit(struct extent_io_tree *tree, u64 start, u64 end,
132 u64 start);
143 unsigned long start, unsigned long len);
145 unsigned long start, unsigned long len);
147 unsigned long start, unsigned long len);
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/u-boot/include/linux/
A Dioport.h19 resource_size_t start; member
131 return res->end - res->start + 1; in resource_size()
139 #define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0) argument
140 #define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (n… argument
141 #define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0) argument
147 resource_size_t start,
152 #define release_region(start,n) __release_region(&ioport_resource, (start), (n)) argument
153 #define check_mem_region(start,n) __check_region(&iomem_resource, (start), (n)) argument
154 #define release_mem_region(start,n) __release_region(&iomem_resource, (start), (n)) argument
168 #define devm_request_region(dev,start,n,name) \ argument
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A Dbitmap.h17 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) argument
51 unsigned long *p = map + BIT_WORD(start); in __bitmap_set()
52 const unsigned int size = start + len; in __bitmap_set()
72 unsigned long *p = map + BIT_WORD(start); in __bitmap_clear()
73 const unsigned int size = start + len; in __bitmap_clear()
165 unsigned long start, in bitmap_find_next_zero_area() argument
182 start = i + 1; in bitmap_find_next_zero_area()
219 __set_bit(start, map); in bitmap_set()
226 __bitmap_set(map, start, nbits); in bitmap_set()
233 __clear_bit(start, map); in bitmap_clear()
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/u-boot/lib/
A Dmembuff.c18 mb->head = mb->start; in membuff_purge()
19 mb->tail = mb->start; in membuff_purge()
29 *data = &mb->start; in membuff_putrawflex()
33 if (!mb->start) in membuff_putrawflex()
144 (int)(mb->tail - mb->start), (int)(*data - mb->start), len); in membuff_getraw()
239 (int)(mb->head - mb->start), (int)(mb->tail - mb->start), in membuff_makecontig()
261 memmove(mb->start + topsize, mb->start, botsize); in membuff_makecontig()
307 s = mb->start; in membuff_readline()
349 mb->start = ptr; in membuff_extend_by()
364 mb->start = buff; in membuff_init()
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/u-boot/arch/arm/cpu/arm926ejs/
A Dcache.c28 void invalidate_dcache_range(unsigned long start, unsigned long stop) in invalidate_dcache_range() argument
30 if (!check_cache_range(start, stop)) in invalidate_dcache_range()
33 while (start < stop) { in invalidate_dcache_range()
34 asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); in invalidate_dcache_range()
35 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
39 void flush_dcache_range(unsigned long start, unsigned long stop) in flush_dcache_range() argument
41 if (!check_cache_range(start, stop)) in flush_dcache_range()
44 while (start < stop) { in flush_dcache_range()
45 asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); in flush_dcache_range()
46 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
/u-boot/arch/arm/mach-uniphier/arm32/
A Dcache-uniphier.c106 writel(start, UNIPHIER_SSCOQAD); in uniphier_cache_maint_common()
137 start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1); in uniphier_cache_maint_range()
139 size = end - start; in uniphier_cache_maint_range()
159 start += chunk_size; in uniphier_cache_maint_range()
168 uniphier_cache_maint_range(start, end, ways, in uniphier_cache_prefetch_range()
175 uniphier_cache_maint_range(start, end, ways, in uniphier_cache_touch_range()
251 if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) { in v7_outer_cache_inval_range()
252 start &= ~(UNIPHIER_SSC_LINE_SIZE - 1); in v7_outer_cache_inval_range()
255 start += UNIPHIER_SSC_LINE_SIZE; in v7_outer_cache_inval_range()
258 if (start >= end) { in v7_outer_cache_inval_range()
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/u-boot/arch/arm/cpu/arm11/
A Dcpu.c75 void invalidate_dcache_range(unsigned long start, unsigned long stop) in invalidate_dcache_range() argument
77 if (!check_cache_range(start, stop)) in invalidate_dcache_range()
80 while (start < stop) { in invalidate_dcache_range()
81 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); in invalidate_dcache_range()
82 start += CONFIG_SYS_CACHELINE_SIZE; in invalidate_dcache_range()
86 void flush_dcache_range(unsigned long start, unsigned long stop) in flush_dcache_range() argument
88 if (!check_cache_range(start, stop)) in flush_dcache_range()
91 while (start < stop) { in flush_dcache_range()
92 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); in flush_dcache_range()
93 start += CONFIG_SYS_CACHELINE_SIZE; in flush_dcache_range()
/u-boot/disk/
A Ddisk-uclass.c81 if (start >= part->gpt_part_info.size) in part_blk_read()
85 blkcnt = part->gpt_part_info.size - start; in part_blk_read()
86 start += part->gpt_part_info.start; in part_blk_read()
104 if (start >= part->gpt_part_info.size) in part_blk_write()
108 blkcnt = part->gpt_part_info.size - start; in part_blk_write()
109 start += part->gpt_part_info.start; in part_blk_write()
127 if (start >= part->gpt_part_info.size) in part_blk_erase()
132 start += part->gpt_part_info.start; in part_blk_erase()
134 return ops->erase(parent, start, blkcnt); in part_blk_erase()
188 start_in_disk = start; in disk_blk_read()
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/u-boot/arch/arm/mach-imx/imx8/
A Dcpu.c315 if (start >= phys_sdram_1_start && start <= end1 && in get_effective_memsize()
347 start = roundup(start, MEMSTART_ALIGNMENT); in dram_init()
349 if (start > end) in dram_init()
352 if (start >= phys_sdram_1_start && start <= end1) { in dram_init()
383 start = gd->bd->bi_dram[current_bank - 1].start; in dram_bank_sort()
391 gd->bd->bi_dram[current_bank].start = start; in dram_bank_sort()
415 start = roundup(start, MEMSTART_ALIGNMENT); in dram_init_banksize()
419 if (start >= phys_sdram_1_start && start <= end1) { in dram_init_banksize()
420 gd->bd->bi_dram[i].start = start; in dram_init_banksize()
430 } else if (start >= phys_sdram_2_start && start <= end2) { in dram_init_banksize()
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/u-boot/arch/arm/mach-exynos/
A Dpinmux.c39 for (i = start; i < start + count; i++) { in exynos5_uart_config()
71 for (i = start; i < start + count; i++) { in exynos5420_uart_config()
116 for (i = start; i < (start + 2); i++) { in exynos5_mmc_config()
121 for (i = (start + 3); i <= (start + 6); i++) { in exynos5_mmc_config()
148 start = 0; in exynos5420_mmc_config()
167 for (i = start; i < (start + 3); i++) { in exynos5420_mmc_config()
187 for (i = (start + 3); i <= (start + 6); i++) { in exynos5420_mmc_config()
647 for (i = start; i < (start + 7); i++) { in exynos4_mmc_config()
691 for (i = start; i < (start + count); i++) { in exynos4_uart_config()
762 for (i = start; i < (start + 7); i++) { in exynos4x12_mmc_config()
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/u-boot/arch/arm/lib/
A Dcache.c22 __weak void flush_cache(unsigned long start, unsigned long size) in flush_cache() argument
24 flush_dcache_range(start, start + size); in flush_cache()
49 __weak void flush_dcache_range(unsigned long start, unsigned long stop) in flush_dcache_range() argument
54 int check_cache_range(unsigned long start, unsigned long stop) in check_cache_range() argument
58 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) in check_cache_range()
66 start, stop); in check_cache_range()
92 phys_addr_t start, end; in noncached_init() local
98 start = end - size; in noncached_init()
100 debug("mapping memory %pa-%pa non-cached\n", &start, &end); in noncached_init()
102 noncached_start = start; in noncached_init()
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A Dcache-pl310.c52 void v7_outer_cache_flush_range(u32 start, u32 stop) in v7_outer_cache_flush_range() argument
61 start &= ~(line_size - 1); in v7_outer_cache_flush_range()
63 for (pa = start; pa < stop; pa = pa + line_size) in v7_outer_cache_flush_range()
70 void v7_outer_cache_inval_range(u32 start, u32 stop) in v7_outer_cache_inval_range() argument
79 if (start & (line_size - 1)) { in v7_outer_cache_inval_range()
81 __func__, start); in v7_outer_cache_inval_range()
83 start = (start + line_size - 1) & ~(line_size - 1); in v7_outer_cache_inval_range()
97 for (pa = start; pa < stop; pa = pa + line_size) in v7_outer_cache_inval_range()
/u-boot/post/drivers/
A Dmemory.c275 ulong *mem = (ulong *) start; in memory_post_test1()
304 ulong *mem = (ulong *) start; in memory_post_test2()
333 ulong *mem = (ulong *) start; in memory_post_test3()
362 ulong *mem = (ulong *) start; in memory_post_test4()
395 ret = memory_post_addrline((ulong *)start, (ulong *)start, in memory_post_test_lines()
400 (ulong *)start, size); in memory_post_test_lines()
422 ret = memory_post_test2(start, size); in memory_post_test_patterns()
425 ret = memory_post_test3(start, size); in memory_post_test_patterns()
428 ret = memory_post_test4(start, size); in memory_post_test_patterns()
455 ret = memory_post_test_lines(start, size); in memory_post_tests()
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/u-boot/test/
A Dtime_ut.c15 ulong base, start, next, diff; in test_get_timer() local
19 start = get_timer(0); in test_get_timer()
23 } while (start == next); in test_get_timer()
25 if (start + 1 != next) { in test_get_timer()
30 start++; in test_get_timer()
85 ulong start; in test_time_comparison() local
87 start = get_timer(0); in test_time_comparison()
89 while (get_timer(start) < 1000) in test_time_comparison()
105 ulong start, delta; in test_udelay() local
108 start = get_timer(0); in test_udelay()
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/u-boot/drivers/mmc/
A Dmmc_write.c25 end = start + blkcnt - 1; in mmc_erase_t()
27 end = (start + blkcnt - 1) * mmc->write_bl_len; in mmc_erase_t()
28 start *= mmc->write_bl_len; in mmc_erase_t()
40 cmd.cmdarg = start; in mmc_erase_t()
115 ((start + blkcnt + mmc->erase_grp_size - 1) in mmc_berase()
149 if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { in mmc_write_blocks()
151 start + blkcnt, mmc_get_blk_desc(mmc)->lba); in mmc_write_blocks()
163 cmd.cmdarg = start; in mmc_write_blocks()
165 cmd.cmdarg = start * mmc->write_bl_len; in mmc_write_blocks()
228 if (mmc_write_blocks(mmc, start, cur, src) != cur) in mmc_bwrite()
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/u-boot/drivers/block/
A Dblkcache.c24 lbaint_t start; member
59 (node->start <= start) && in cache_find()
60 (node->start + node->blkcnt >= start + blkcnt)) { in cache_find()
72 lbaint_t start, lbaint_t blkcnt, in blkcache_read() argument
78 const char *src = node->cache + (start - node->start) * blksz; in blkcache_read()
81 start, blkcnt); in blkcache_read()
87 start, blkcnt); in blkcache_read()
93 lbaint_t start, lbaint_t blkcnt, in blkcache_fill() argument
113 node->start, node->blkcnt); in blkcache_fill()
134 start, blkcnt); in blkcache_fill()
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/u-boot/arch/arm/mach-rmobile/
A Dmemmap-gen3.c60 u64 start, size; in enable_caches() local
74 start = gd->bd->bi_dram[bank].start; in enable_caches()
82 if (start >> 32ULL) in enable_caches()
86 if (start == 0x48000000) { in enable_caches()
95 start = 0x47E00000ULL; in enable_caches()
99 gen3_mem_map[i].virt = start; in enable_caches()
100 gen3_mem_map[i].phys = start; in enable_caches()
118 start = gd->bd->bi_dram[bank].start; in enable_caches()
126 if (!(start >> 32ULL)) in enable_caches()
129 gen3_mem_map[i].virt = start; in enable_caches()
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/u-boot/include/
A Dblk.h88 lbaint_t start,
92 lbaint_t start,
96 lbaint_t start,
126 lbaint_t start, lbaint_t blkcnt,
142 lbaint_t start, lbaint_t blkcnt,
186 lbaint_t start, lbaint_t blkcnt, in blkcache_read() argument
193 lbaint_t start, lbaint_t blkcnt, in blkcache_fill() argument
217 unsigned long (*read)(struct udevice *dev, lbaint_t start,
518 start, blkcnt, block_dev->blksz, buffer)) in blk_dread()
529 start, blkcnt, block_dev->blksz, buffer); in blk_dread()
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/u-boot/cmd/
A Diotrace.c12 ulong start, size, needed_size, offset, count; in do_print_stats() local
15 iotrace_get_buffer(&start, &size, &needed_size, &offset, &count); in do_print_stats()
16 printf("Start: %08lx\n", start); in do_print_stats()
19 iotrace_get_region(&start, &size); in do_print_stats()
20 printf("Region: %08lx\n", start); in do_print_stats()
23 printf("Output: %08lx\n", start + offset); in do_print_stats()
30 ulong start, size, needed_size, offset, count; in do_print_trace() local
34 iotrace_get_buffer(&start, &size, &needed_size, &offset, &count); in do_print_trace()
36 if (!start || !size || !count) in do_print_trace()
41 cur_record = (struct iotrace_record *)start; in do_print_trace()
A Dini.c125 char *start; in ini_parse() local
136 start = lskip(rstrip(line)); in ini_parse()
138 if (*start == ';' || *start == '#') { in ini_parse()
145 else if (*prev_name && *start && start > line) { in ini_parse()
155 else if (*start == '[') { in ini_parse()
157 end = find_char_or_comment(start + 1, ']'); in ini_parse()
160 strncpy0(section, start + 1, sizeof(section)); in ini_parse()
166 } else if (*start && *start != ';') { in ini_parse()
168 end = find_char_or_comment(start, '='); in ini_parse()
170 end = find_char_or_comment(start, ':'); in ini_parse()
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