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Searched refs:t2 (Results 1 – 25 of 30) sorted by relevance

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/u-boot/arch/mips/mach-ath79/ar933x/
A Dlowlevel_init.S88 and t1, t1, t2
95 li t2, 0x20
97 beqz t2, 1b
99 addi t2, t2, -1
150 and t1, t1, t2
152 or t1, t1, t2
191 and t1, t1, t2
217 and t1, t1, t2
240 li t2, 10
242 subu t2, t2, 1
[all …]
/u-boot/board/imgtec/malta/
A Dlowlevel_init.S111 li t2, MSC01_PBC_CS0CFG_DTYP_MSK
112 and t1, t2
121 li t2, -CFG_SYS_SDRAM_SIZE
123 sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
125 sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
129 li t2, -MALTA_MSC01_IP1_SIZE
137 li t2, -MALTA_MSC01_IP2_SIZE1
141 li t2, -MALTA_MSC01_IP2_SIZE2
147 li t2, -MALTA_MSC01_IP3_SIZE
224 li t2, MSC01_PCI_CFG_RA_MSK | \
[all …]
/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S53 li t2, 0x00000000
54 or t3, t1, t2
95 li t2, 0x1
99 and t1, t1, t2
105 and t2, t1, t4
106 srl t2, t2, 0x1 /* no. of Pass Runs */
131 li t2, 0xaa55aa55
154 li t2, 0x3f
155 beq t1, t2, _STOP_TEST
177 lw t2, 0x4(t0)
[all …]
/u-boot/board/CZ.NIC/turris_mox/
A Dmox_sp.c35 static inline void res_to_mac(u8 *mac, u32 t1, u32 t2) in res_to_mac() argument
39 mac[2] = t2 >> 24; in res_to_mac()
40 mac[3] = t2 >> 16; in res_to_mac()
41 mac[4] = t2 >> 8; in res_to_mac()
42 mac[5] = t2; in res_to_mac()
/u-boot/arch/mips/mach-octeon/
A Dlowlevel_init.S63 PTR_LA t2, _end
64 daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
65 daddiu t2, t2, 127
66 ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
80 bne t1, t2, 1b
/u-boot/arch/powerpc/lib/
A D_ashrdi3.S38 sraw r7,r3,r7 # t2 = MSW >> (count-32)
40 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
42 or r4,r4,r7 # LSW |= t2
A D_ashldi3.S37 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
40 or r3,r3,r7 # MSW |= t2
A D_lshrdi3.S37 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
40 or r4,r4,r7 # LSW |= t2
/u-boot/lib/
A Dsha512.c144 uint64_t a, b, c, d, e, f, g, h, t1, t2; in sha512_transform() local
170 t2 = e0(a) + Maj(a,b,c); d+=t1; h=t1+t2; in sha512_transform()
172 t2 = e0(h) + Maj(h,a,b); c+=t1; g=t1+t2; in sha512_transform()
174 t2 = e0(g) + Maj(g,h,a); b+=t1; f=t1+t2; in sha512_transform()
176 t2 = e0(f) + Maj(f,g,h); a+=t1; e=t1+t2; in sha512_transform()
178 t2 = e0(e) + Maj(e,f,g); h+=t1; d=t1+t2; in sha512_transform()
180 t2 = e0(d) + Maj(d,e,f); g+=t1; c=t1+t2; in sha512_transform()
182 t2 = e0(c) + Maj(c,d,e); f+=t1; b=t1+t2; in sha512_transform()
184 t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2; in sha512_transform()
191 a = b = c = d = e = f = g = h = t1 = t2 = 0; in sha512_transform()
/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S103 li t2, 0x08000000
104 or t1, t1, t2
108 li t2, 0xf7ffffff
109 and t1, t1, t2
153 li t2, ~QCA953X_PLL_CONFIG_PWD
154 and t1, t1, t2
159 li t2, ~QCA953X_PLL_CONFIG_PWD
160 and t1, t1, t2
165 li t2, ~PLL_CLK_CTRL_PLL_BYPASS
166 and t1, t1, t2
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S30 li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)
40 lw t3, 0(t2)
47 lw t3, 0(t2)
53 sw t3, 0(t2)
55 li t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG)
56 lw t3, 0(t2)
60 sw t3, 0(t2)
/u-boot/arch/riscv/cpu/
A Dstart.S177 LREG t2, GD_AVAILABLE_HARTS(gp)
178 or t2, t2, t1
179 SREG t2, GD_AVAILABLE_HARTS(gp)
287 la t2, __bss_start /* t2 <- source end address */
294 blt t0, t2, copy_loop
301 la t2, __rel_dyn_end
302 beq t1, t2, clear_bss
304 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
339 blt t1, t2, 6b
/u-boot/arch/mips/lib/
A Dcache_init.S168 li t2, 2
169 sllv R_L2_LINE, t2, R_L2_LINE
171 ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
172 addiu t2, t2, 1
173 mul R_L2_SIZE, R_L2_LINE, t2
175 ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
176 sllv R_L2_SIZE, R_L2_SIZE, t2
177 li t2, 64
178 mul R_L2_SIZE, R_L2_SIZE, t2
405 li t2, GCR_REV_CM3
[all …]
/u-boot/arch/mips/cpu/
A Dcm_init.S35 PTR_LI t2, CKSEG1
36 PTR_ADDU t0, t0, t2
A Dstart.S51 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
53 sp, sp, t2 # reserve space for early malloc
/u-boot/arch/mips/mach-mtmips/mt7621/spl/
A Dlaunch_ll.S42 move t2, zero
45 sll t1, t2, GCR_Cx_OTHER_CORENUM_SHIFT
52 addiu t2, 1
53 bne t2, a0, _next_coherent_core
103 mfc0 t2, CP0_COUNT
104 subu t2, t1
105 bltz t2, time_wait
A Dstart.S42 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
44 sp, sp, t2 # reserve space for early malloc
158 li t2, 1
159 ins t1, t2, CPU_CLK_SEL_S, 2
/u-boot/arch/mips/include/asm/
A Dregdef.h29 #define t2 $10 macro
80 #define t2 $14 macro
/u-boot/scripts/coccinelle/null/
A Dbadzero.cocci148 @t2 depends on !patch disable is_zero,isnt_zero @
171 p << t2.p1;
177 p << t2.p2;
183 p << t2.p1;
189 p << t2.p2;
/u-boot/arch/arm/include/asm/arch-omap3/
A Dmmc_host_def.h33 typedef struct t2 { struct
/u-boot/lib/libavb/
A Davb_sha256.c60 t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \
62 wv[h] = t1 + t2; \
114 uint32_t t1, t2; in SHA256_transform() local
141 t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); in SHA256_transform()
149 wv[0] = t1 + t2; in SHA256_transform()
A Davb_sha512.c62 t2 = SHA512_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \
64 wv[h] = t1 + t2; \
133 uint64_t t1, t2; in SHA512_transform() local
277 t2 = SHA512_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); in SHA512_transform()
285 wv[0] = t1 + t2; in SHA512_transform()
/u-boot/arch/mips/mach-mtmips/mt7621/tpl/
A Dstart.S131 li t2, GCR_CONTROL_SYNCCTL
132 or t1, t1, t2
/u-boot/arch/riscv/lib/
A Dmemcpy.S68 REG_L t2, 7*SZREG(a1)
79 REG_S t2, 7*SZREG(a0)
/u-boot/arch/riscv/include/asm/
A Dptrace.h20 unsigned long t2; member

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