| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h616_ddr3_1333.c | 49 u8 tcwl = 5; /* JEDEC: 8 */ in mctl_set_timing_params() local
59 tcwl = 4; in mctl_set_timing_params()
64 twtp = tcl + 2 + tcwl; in mctl_set_timing_params()
65 twr2rd = trtp + 2 + tcwl; in mctl_set_timing_params()
66 trd2wr = tcl + 3 - tcwl; in mctl_set_timing_params()
72 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
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| A D | ddr2_v3s.c | 34 u8 tcwl = 3; /* CWL 6 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| A D | ddr3_1333.c | 34 u8 tcwl = 4; /* CWL 8 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 34 u8 tcwl = 3; /* CWL 6 */ in mctl_set_timing_params() local
43 u8 twtp = tcwl + 4 + twr + 1; in mctl_set_timing_params()
44 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params()
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params()
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| A D | h6_lpddr3.c | 65 u8 tcwl = 3; /* CWL 6 */ in mctl_set_timing_params() local
73 u8 twtp = tcwl + 4 + twr + 1; in mctl_set_timing_params()
79 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params()
80 u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; in mctl_set_timing_params()
90 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
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| A D | h6_ddr3_1333.c | 79 u8 tcwl = 4; /* JEDEC: 8 */ in mctl_set_timing_params() local
87 u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */ in mctl_set_timing_params()
88 u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */ in mctl_set_timing_params()
102 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 119 u8 tcwl = 4; /* CWL 8 */ in auto_set_timing_para() local
128 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in auto_set_timing_para()
129 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
130 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
161 tcwl = 3; /* CWL 8 */ in auto_set_timing_para()
167 twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */ in auto_set_timing_para()
168 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
169 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
176 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 119 u8 tcwl = 4; /* CWL 8 */ in auto_set_timing_para() local
128 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in auto_set_timing_para()
129 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
130 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
144 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| A D | dram_sun6i.c | 216 writel(MCTL_TCWL, &mctl_ctl->tcwl); in mctl_channel_init()
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| /u-boot/drivers/ram/rockchip/ |
| A D | dmc-rk3368.c | 160 u32 tcl, u32 tal, u32 tcwl) in ddrphy_config() argument
170 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); in ddrphy_config()
246 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); in memory_init()
478 pctl_timing->tcwl = 10; in pctl_calc_timings()
481 pctl_timing->tcwl = 6; in pctl_calc_timings()
484 pctl_timing->tcwl = 7; in pctl_calc_timings()
487 pctl_timing->tcwl = 8; in pctl_calc_timings()
498 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; in pctl_calc_timings()
565 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
837 params->pctl_timing.tcwl); in setup_sdram()
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| A D | sdram_rk322x.c | 432 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
446 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
499 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); in phy_cfg()
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| A D | sdram_rk3288.c | 257 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
278 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
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| A D | sdram_rk3066.c | 234 writel(sdram_params->pctl_timing.tcwl - 1, in rk3066_dmc_pctl_cfg()
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| A D | sdram_rk3188.c | 245 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 49 u32 tcwl; member
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| A D | sdram_rk3036.h | 50 u32 tcwl; member
247 u32 tcwl; member
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| A D | sdram_rk322x.h | 83 u32 tcwl; member
209 u32 tcwl; member
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| A D | ddr_rk3368.h | 60 u32 tcwl; member
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| A D | ddr_rk3288.h | 51 u32 tcwl; member
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1285 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1305 tcwl = 4; in mx6_ddr3_cfg()
1312 tcwl = 3; in mx6_ddr3_cfg()
1326 todtlon = tcwl; in mx6_ddr3_cfg()
1327 taxpd = tcwl; in mx6_ddr3_cfg()
1328 tanpd = tcwl; in mx6_ddr3_cfg()
1423 debug("tcwl=%d\n", tcwl); in mx6_ddr3_cfg()
1501 (twr << 9) | (tmrd << 5) | tcwl; in mx6_ddr3_cfg()
1546 ((tcwl - 3) & 3) << 3; in mx6_ddr3_cfg()
1612 ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) | in mx6_ddr3_cfg()
[all …]
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun6i.h | 83 u32 tcwl; /* 0xec */ member
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 65 tcwl
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| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| A D | sdram_rk3036.c | 613 reg = readl(&pctl->tcwl); in pctl_cfg()
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