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Searched refs:timing (Results 1 – 25 of 205) sorted by relevance

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/u-boot/drivers/video/tegra20/
A Dmipi-phy.c28 timing->eot = 0; in mipi_dphy_timing_get_default()
50 timing->taget = 5 * timing->lpx; in mipi_dphy_timing_get_default()
51 timing->tago = 4 * timing->lpx; in mipi_dphy_timing_get_default()
52 timing->tasure = 2 * timing->lpx; in mipi_dphy_timing_get_default()
74 if (timing->clkprepare < 38 || timing->clkprepare > 95) in mipi_dphy_timing_validate()
77 if (timing->clksettle < 95 || timing->clksettle > 300) in mipi_dphy_timing_validate()
86 if (timing->clkprepare + timing->clkzero < 300) in mipi_dphy_timing_validate()
102 if (timing->hsprepare + timing->hszero < 145 + 10 * period) in mipi_dphy_timing_validate()
121 if (timing->taget != 5 * timing->lpx) in mipi_dphy_timing_validate()
124 if (timing->tago != 4 * timing->lpx) in mipi_dphy_timing_validate()
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/u-boot/drivers/video/
A Datmel_lcdfb.c33 struct display_timing timing; member
72 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
94 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_fb_init()
104 value |= timing->vfront_porch.typ; in atmel_fb_init()
112 value |= (timing->hback_porch.typ - 1); in atmel_fb_init()
117 value |= timing->vactive.typ - 1; in atmel_fb_init()
151 struct display_timing *timing = &priv->timing; in atmel_fb_lcd_probe() local
160 uc_priv->xsize = timing->hactive.typ; in atmel_fb_lcd_probe()
161 uc_priv->ysize = timing->vactive.typ; in atmel_fb_lcd_probe()
174 struct display_timing *timing = &priv->timing; in atmel_fb_of_to_plat() local
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A Datmel_hlcdfb.c35 struct display_timing timing; member
75 struct display_timing *timing = &priv->timing; in atmel_hlcdc_init() local
106 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
107 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
270 uc_priv->xsize = priv->timing.hactive.typ; in atmel_hlcdc_probe()
271 uc_priv->ysize = priv->timing.vactive.typ; in atmel_hlcdc_probe()
293 0, &priv->timing)) { in atmel_hlcdc_of_to_plat()
298 if (priv->timing.hactive.typ > LCD_MAX_WIDTH) in atmel_hlcdc_of_to_plat()
299 priv->timing.hactive.typ = LCD_MAX_WIDTH; in atmel_hlcdc_of_to_plat()
301 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT) in atmel_hlcdc_of_to_plat()
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A Ddisplay-uclass.c24 const struct display_timing *timing) in display_enable() argument
32 ret = ops->enable(dev, panel_bpp, timing); in display_enable()
42 static bool display_mode_valid(void *priv, const struct display_timing *timing) in display_mode_valid() argument
48 return ops->mode_valid(dev, timing); in display_mode_valid()
53 int display_read_timing(struct udevice *dev, struct display_timing *timing) in display_read_timing() argument
61 return ops->read_timing(dev, timing); in display_read_timing()
69 return edid_get_timing_validate(buf, ret, timing, in display_read_timing()
A Dvideomodes.c449 struct display_timing *timing) in video_ctfb_mode_to_display_timing() argument
453 timing->hactive.typ = mode->xres; in video_ctfb_mode_to_display_timing()
456 timing->hsync_len.typ = mode->hsync_len; in video_ctfb_mode_to_display_timing()
458 timing->vactive.typ = mode->yres; in video_ctfb_mode_to_display_timing()
461 timing->vsync_len.typ = mode->vsync_len; in video_ctfb_mode_to_display_timing()
463 timing->flags = 0; in video_ctfb_mode_to_display_timing()
466 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; in video_ctfb_mode_to_display_timing()
468 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; in video_ctfb_mode_to_display_timing()
470 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; in video_ctfb_mode_to_display_timing()
472 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; in video_ctfb_mode_to_display_timing()
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A Dtda19988.c390 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ + in tda19988_enable()
391 timing->hactive.typ + timing->hfront_porch.typ; in tda19988_enable()
392 lines = timing->vsync_len.typ + timing->vback_porch.typ + in tda19988_enable()
393 timing->vactive.typ + timing->vfront_porch.typ; in tda19988_enable()
458 timing->vfront_porch.typ); in tda19988_enable()
460 timing->hfront_porch.typ); in tda19988_enable()
462 timing->vfront_porch.typ + in tda19988_enable()
463 timing->vsync_len.typ); in tda19988_enable()
465 timing->hfront_porch.typ); in tda19988_enable()
471 timing->hfront_porch.typ); in tda19988_enable()
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/u-boot/drivers/video/tegra124/
A Ddisplay.c31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
59 print_mode(timing); in update_display_mode()
66 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
75 writel(timing->hactive.typ | (timing->vactive.typ << 16), in update_display_mode()
236 writel(((timing->vactive.typ << 16) | timing->hactive.typ), in update_window()
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A Ddp.c484 const struct display_timing *timing, in tegra_dc_dp_calc_config() argument
518 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
622 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config()
623 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
654 const struct display_timing *timing, in tegra_dc_dp_init_max_link_cfg() argument
1308 const struct display_timing *timing, in tegra_dp_do_link_training() argument
1353 const struct display_timing *timing) in tegra_dc_dp_explore_link_cfg() argument
1357 if (!timing->pixelclock.typ || !timing->hactive.typ || in tegra_dc_dp_explore_link_cfg()
1358 !timing->vactive.typ) { in tegra_dc_dp_explore_link_cfg()
1426 const struct display_timing *timing) in tegra_dc_dp_check_sink() argument
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/u-boot/board/samsung/common/
A Dsromc.c28 u32 timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ in exyno5_sromc_probe() local
45 ret = dev_read_u32_array(dev, "srom-timing", timing, in exyno5_sromc_probe()
51 smc_bc_conf = SROMC_BC_TACS(timing[FDT_SROM_TACS]) | in exyno5_sromc_probe()
52 SROMC_BC_TCOS(timing[FDT_SROM_TCOS]) | in exyno5_sromc_probe()
53 SROMC_BC_TACC(timing[FDT_SROM_TACC]) | in exyno5_sromc_probe()
54 SROMC_BC_TCOH(timing[FDT_SROM_TCOH]) | in exyno5_sromc_probe()
55 SROMC_BC_TAH(timing[FDT_SROM_TAH]) | in exyno5_sromc_probe()
56 SROMC_BC_TACP(timing[FDT_SROM_TACP]) | in exyno5_sromc_probe()
57 SROMC_BC_PMC(timing[FDT_SROM_PMC]); in exyno5_sromc_probe()
/u-boot/common/
A Dedid.c105 set_entry(&timing->hactive, ha); in decode_timing()
106 set_entry(&timing->hfront_porch, hso); in decode_timing()
108 set_entry(&timing->hsync_len, hspw); in decode_timing()
110 set_entry(&timing->vactive, va); in decode_timing()
113 set_entry(&timing->vsync_len, vspw); in decode_timing()
115 timing->flags = 0; in decode_timing()
131 timing->pixelclock.typ, in decode_timing()
173 struct display_timing *timing, in edid_find_valid_timing() argument
184 decode_timing((u8 *)t, timing); in edid_find_valid_timing()
187 timing); in edid_find_valid_timing()
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/u-boot/test/dm/
A Dtest-fdt.c1088 struct display_timing timing; in dm_test_decode_display_timing() local
1094 ut_assert(timing.hactive.typ == 240); in dm_test_decode_display_timing()
1097 ut_assert(timing.hsync_len.typ == 1); in dm_test_decode_display_timing()
1098 ut_assert(timing.vactive.typ == 320); in dm_test_decode_display_timing()
1101 ut_assert(timing.vsync_len.typ == 2); in dm_test_decode_display_timing()
1116 ut_assert(timing.hactive.typ == 480); in dm_test_decode_display_timing()
1120 ut_assert(timing.vactive.typ == 800); in dm_test_decode_display_timing()
1138 ut_assert(timing.hactive.typ == 800); in dm_test_decode_display_timing()
1142 ut_assert(timing.vactive.typ == 480); in dm_test_decode_display_timing()
1168 struct display_timing timing; in dm_test_decode_panel_timing() local
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/u-boot/drivers/video/ti/
A Dtilcdc-panel.c22 struct display_timing timing; member
63 struct display_timing *timing) in tilcdc_panel_get_display_timing() argument
67 memcpy(timing, &priv->timing, sizeof(*timing)); in tilcdc_panel_get_display_timing()
108 err = ofnode_decode_display_timing(dev_ofnode(dev), 0, &priv->timing); in tilcdc_panel_of_to_plat()
140 priv->timing.hactive.typ, priv->timing.vactive.typ, in tilcdc_panel_of_to_plat()
141 priv->info.bpp, priv->timing.pixelclock.typ); in tilcdc_panel_of_to_plat()
143 priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ, in tilcdc_panel_of_to_plat()
144 priv->timing.hsync_len.typ); in tilcdc_panel_of_to_plat()
146 priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ, in tilcdc_panel_of_to_plat()
147 priv->timing.vsync_len.typ); in tilcdc_panel_of_to_plat()
A Dtilcdc.c176 struct display_timing timing; in tilcdc_probe() local
199 timing.pixelclock.typ); in tilcdc_probe()
203 if (timing.hactive.typ > LCDC_MAX_WIDTH) in tilcdc_probe()
204 timing.hactive.typ = LCDC_MAX_WIDTH; in tilcdc_probe()
206 if (timing.vactive.typ > LCDC_MAX_HEIGHT) in tilcdc_probe()
207 timing.vactive.typ = LCDC_MAX_HEIGHT; in tilcdc_probe()
291 reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3; in tilcdc_probe()
339 if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) in tilcdc_probe()
342 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) in tilcdc_probe()
373 uc_priv->xsize = timing.hactive.typ; in tilcdc_probe()
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/u-boot/include/
A Ddisplay.h32 int display_read_timing(struct udevice *dev, struct display_timing *timing);
43 const struct display_timing *timing);
61 int (*read_timing)(struct udevice *dev, struct display_timing *timing);
82 const struct display_timing *timing);
92 const struct display_timing *timing);
/u-boot/drivers/video/rockchip/
A Drk_mipi.c29 struct display_timing *timing) in rk_mipi_read_timing() argument
33 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing); in rk_mipi_read_timing()
78 const struct display_timing *timing) in rk_mipi_dsi_enable() argument
90 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
92 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
93 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
94 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
95 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
101 val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0; in rk_mipi_dsi_enable()
104 val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0; in rk_mipi_dsi_enable()
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/u-boot/drivers/mmc/
A Dxenon_sdhci.c125 u8 timing; member
149 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
410 priv->timing = MMC_TIMING_UHS_DDR50; in xenon_sdhci_set_ios_post()
412 priv->timing = MMC_TIMING_UHS_SDR25; in xenon_sdhci_set_ios_post()
414 priv->timing = MMC_TIMING_UHS_SDR50; in xenon_sdhci_set_ios_post()
417 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
419 priv->timing = MMC_TIMING_SD_HS; in xenon_sdhci_set_ios_post()
424 priv->timing = MMC_TIMING_MMC_DDR52; in xenon_sdhci_set_ios_post()
426 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
428 priv->timing = MMC_TIMING_MMC_HS; in xenon_sdhci_set_ios_post()
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/u-boot/drivers/video/meson/
A Dmeson_dw_hdmi.c182 struct display_timing timing; in meson_dw_hdmi_read_edid() local
199 timing.hactive.typ, timing.hfront_porch.typ, in meson_dw_hdmi_read_edid()
200 timing.hback_porch.typ, timing.hsync_len.typ, in meson_dw_hdmi_read_edid()
201 timing.vactive.typ, timing.vfront_porch.typ, in meson_dw_hdmi_read_edid()
202 timing.vback_porch.typ, timing.vsync_len.typ); in meson_dw_hdmi_read_edid()
204 if (timing.flags & DISPLAY_FLAGS_INTERLACED) in meson_dw_hdmi_read_edid()
206 if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN) in meson_dw_hdmi_read_edid()
208 if (timing.flags & DISPLAY_FLAGS_DOUBLECLK) in meson_dw_hdmi_read_edid()
210 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) in meson_dw_hdmi_read_edid()
212 if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH) in meson_dw_hdmi_read_edid()
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A Dmeson_vpu.c49 struct display_timing timing; in meson_vpu_setup_mode() local
54 ret = display_read_timing(disp, &timing); in meson_vpu_setup_mode()
60 uc_priv->xsize = timing.hactive.typ; in meson_vpu_setup_mode()
61 uc_priv->ysize = timing.vactive.typ; in meson_vpu_setup_mode()
63 ret = display_enable(disp, 0, &timing); in meson_vpu_setup_mode()
70 timing.flags = DISPLAY_FLAGS_INTERLACED; in meson_vpu_setup_mode()
91 meson_vpu_setup_plane(dev, timing.flags & DISPLAY_FLAGS_INTERLACED); in meson_vpu_setup_mode()
92 meson_vpu_setup_venc(dev, &timing, is_cvbs); in meson_vpu_setup_mode()
93 meson_vpu_setup_vclk(dev, &timing, is_cvbs); in meson_vpu_setup_mode()
/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/
A Dddr.c42 struct dram_timing_info *timing; member
49 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
51 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
53 .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
55 .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
57 .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
59 .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
153 if (ddr_init(lpddr4_array[i].timing)) { in spl_dram_init_compulab()
/u-boot/drivers/usb/host/
A Dehci-tegra.c332 const unsigned *timing; in get_pll_timing() local
337 return timing; in get_pll_timing()
380 const unsigned *timing; in init_utmi_usb_controller() local
422 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
435 timing[PARAM_XTAL_FREQ_COUNT] << in init_utmi_usb_controller()
443 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
456 timing[PARAM_XTAL_FREQ_COUNT] << in init_utmi_usb_controller()
714 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], in config_clock()
715 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); in config_clock()
718 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], in config_clock()
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/u-boot/board/friendlyarm/nanopi2/
A Dlcds.c101 .timing = {
128 .timing = {
155 .timing = {
182 .timing = {
209 .timing = {
236 .timing = {
263 .timing = {
289 .timing = {
316 .timing = {
342 .timing = {
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A Dboard.c131 struct nxp_lcd_timing *timing = &lcd->timing; in nx_display_fixup_dp() local
139 sync->h_sync_width = timing->h_sw; in nx_display_fixup_dp()
140 sync->h_back_porch = timing->h_bp; in nx_display_fixup_dp()
141 sync->h_front_porch = timing->h_fp; in nx_display_fixup_dp()
145 sync->v_sync_width = timing->v_sw; in nx_display_fixup_dp()
146 sync->v_back_porch = timing->v_bp; in nx_display_fixup_dp()
147 sync->v_front_porch = timing->v_fp; in nx_display_fixup_dp()
151 div = timing->h_sw + timing->h_bp + timing->h_fp + lcd->width; in nx_display_fixup_dp()
152 div *= timing->v_sw + timing->v_bp + timing->v_fp + lcd->height; in nx_display_fixup_dp()
/u-boot/drivers/ram/
A Dstm32_sdram.c168 struct stm32_sdram_timing *timing; in stm32_sdram_init() local
204 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
205 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
206 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
207 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
208 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
209 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
214 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
215 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
216 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
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/u-boot/drivers/video/sunxi/
A Dsunxi_lcd.c22 struct display_timing timing; member
70 struct display_timing *timing) in sunxi_lcd_read_timing() argument
74 memcpy(timing, &priv->timing, sizeof(struct display_timing)); in sunxi_lcd_read_timing()
101 &priv->timing, &channel_bpp); in sunxi_lcd_probe()
119 0, &priv->timing)) { in sunxi_lcd_probe()
/u-boot/tools/binman/
A Dstate.py485 timing = timing_info.get(threaded_name)
486 if not timing:
487 timing = Timing(threaded_name)
488 timing_info[threaded_name] = timing
489 return timing
497 timing = GetTiming(name)
498 timing.start = time.monotonic()
509 timing = GetTiming(name)
510 timing.accum += time.monotonic() - timing.start
515 for threaded_name, timing in timing_info.items():
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