Searched refs:timing_cfg_0 (Results 1 – 22 of 22) sorted by relevance
| /u-boot/drivers/ddr/fsl/ |
| A D | mpc85xx_ddr_gen2.c | 68 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
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| A D | arm_ddr_gen3.c | 94 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 126 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
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| A D | fsl_ddr_gen4.c | 170 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
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| A D | ctrl_regs.c | 440 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
450 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
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| A D | interactive.c | 633 CFG_REGS(timing_cfg_0), in print_fsl_memctl_config_regs()
724 CFG_REGS(timing_cfg_0), in fsl_ddr_regs_edit()
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| /u-boot/board/socrates/ |
| A D | sdram.c | 39 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 60 .timing_cfg_0 = 0x91550018,
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 27 .timing_cfg_0 = 0x9011010c,
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| /u-boot/board/gdsys/mpc8308/ |
| A D | sdram.c | 55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
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| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 62 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
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| /u-boot/drivers/ram/ |
| A D | mpc83xx_sdram.c | 326 u32 timing_cfg_0; in mpc83xx_sdram_probe() local
584 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | in mpc83xx_sdram_probe()
593 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); in mpc83xx_sdram_probe()
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| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 39 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
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| /u-boot/board/freescale/mpc837xerdb/ |
| A D | mpc837xerdb.c | 116 im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_immap.h | 34 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ member
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| A D | fsl_ddr_sdram.h | 249 unsigned int timing_cfg_0; member
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 221 .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, in fixed_sdram()
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| /u-boot/board/keymile/km83xx/ |
| A D | km83xx.c | 216 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | spd_sdram.c | 475 ddr->timing_cfg_0 = (0 in spd_sdram()
481 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in spd_sdram()
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| /u-boot/board/cssi/cmpcpro/ |
| A D | cmpcpro.c | 309 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in dram_init()
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 154 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | immap_83xx.h | 288 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ member
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