| /u-boot/drivers/ddr/fsl/ |
| A D | mpc85xx_ddr_gen1.c | 48 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 128 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
214 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
339 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
515 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen2.c | 70 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| A D | arm_ddr_gen3.c | 96 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| A D | ctrl_regs.c | 714 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
724 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
1934 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1935 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
2032 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2033 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
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| A D | fsl_ddr_gen4.c | 172 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| A D | interactive.c | 635 CFG_REGS(timing_cfg_2), in print_fsl_memctl_config_regs()
726 CFG_REGS(timing_cfg_2), in fsl_ddr_regs_edit()
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| /u-boot/board/socrates/ |
| A D | sdram.c | 41 ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 62 .timing_cfg_2 = 0x0048C111,
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 30 .timing_cfg_2 = 0x0fc0d118,
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| /u-boot/board/gdsys/mpc8308/ |
| A D | sdram.c | 54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 64 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
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| /u-boot/drivers/ram/ |
| A D | mpc83xx_sdram.c | 337 u32 timing_cfg_2; in mpc83xx_sdram_probe() local
776 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | in mpc83xx_sdram_probe()
784 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); in mpc83xx_sdram_probe()
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| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
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| /u-boot/board/freescale/mpc837xerdb/ |
| A D | mpc837xerdb.c | 118 im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_immap.h | 36 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ member
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| A D | fsl_ddr_sdram.h | 251 unsigned int timing_cfg_2; member
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 223 .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, in fixed_sdram()
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| /u-boot/board/keymile/km83xx/ |
| A D | km83xx.c | 218 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | spd_sdram.c | 630 ddr->timing_cfg_2 = (0 in spd_sdram()
641 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); in spd_sdram()
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| /u-boot/board/cssi/cmpcpro/ |
| A D | cmpcpro.c | 311 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in dram_init()
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 156 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | immap_83xx.h | 290 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ member
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