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Searched refs:timing_cfg_3 (Results 1 – 21 of 21) sorted by relevance

/u-boot/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen2.c67 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
A Darm_ddr_gen3.c93 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
A Dutil.c248 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; in print_ddr_info()
A Dmpc85xx_ddr_gen3.c125 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
A Dfsl_ddr_gen4.c169 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
A Dctrl_regs.c493 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
503 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
A Dinteractive.c632 CFG_REGS(timing_cfg_3), in print_fsl_memctl_config_regs()
723 CFG_REGS(timing_cfg_3), in fsl_ddr_regs_edit()
/u-boot/board/freescale/ls1043ardb/
A Dddr.h59 .timing_cfg_3 = 0x010C1000,
/u-boot/board/kontron/sl28/
A Dddr.c28 .timing_cfg_3 = 0x010c1000,
/u-boot/board/gdsys/mpc8308/
A Dsdram.c52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
/u-boot/board/freescale/ls1021aiot/
A Dls1021aiot.c65 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
/u-boot/board/freescale/ls1021atsn/
A Dls1021atsn.c42 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
/u-boot/board/freescale/mpc837xerdb/
A Dmpc837xerdb.c119 im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; in fixed_sdram()
/u-boot/include/
A Dfsl_immap.h33 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ member
A Dfsl_ddr_sdram.h248 unsigned int timing_cfg_3; member
/u-boot/board/freescale/p1_p2_rdb_pc/
A Dddr.c220 .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, in fixed_sdram()
/u-boot/board/keymile/km83xx/
A Dkm83xx.c219 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
/u-boot/board/cssi/cmpcpro/
A Dcmpcpro.c312 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in dram_init()
/u-boot/board/freescale/ls1021atwr/
A Dls1021atwr.c157 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
/u-boot/arch/powerpc/include/asm/
A Dimmap_83xx.h287 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ member
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c524 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask); in mpc83xx_sdram_probe()

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