Searched refs:timing_info (Results 1 – 5 of 5) sorted by relevance
176 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; in dram_config_save()186 sizeof(*timing_info)); in dram_config_save()190 for (i = 0; i < timing_info->ddrc_cfg_num; i++) { in dram_config_save()191 cfg->reg = timing_info->ddrc_cfg[i].reg; in dram_config_save()192 cfg->val = timing_info->ddrc_cfg[i].val; in dram_config_save()198 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { in dram_config_save()199 cfg->reg = timing_info->ddrphy_cfg[i].reg; in dram_config_save()200 cfg->val = timing_info->ddrphy_cfg[i].val; in dram_config_save()214 for (i = 0; i < timing_info->ddrphy_pie_num; i++) { in dram_config_save()215 cfg->reg = timing_info->ddrphy_pie[i].reg; in dram_config_save()[all …]
222 saved_timing->ctl_cfg_num = timing_info->ctl_cfg_num; in save_dram_config()231 sizeof(*timing_info)); in save_dram_config()235 for (i = 0; i < timing_info->ctl_cfg_num; i++) { in save_dram_config()236 cfg->reg = timing_info->ctl_cfg[i].reg; in save_dram_config()237 cfg->val = timing_info->ctl_cfg[i].val; in save_dram_config()243 for (i = 0; i < timing_info->phy_f1_cfg_num; i++) { in save_dram_config()244 cfg->reg = timing_info->phy_f1_cfg[i].reg; in save_dram_config()245 cfg->val = timing_info->phy_f1_cfg[i].val; in save_dram_config()251 for (i = 0; i < timing_info->phy_f2_cfg_num; i++) { in save_dram_config()252 cfg->reg = timing_info->phy_f2_cfg[i].reg; in save_dram_config()[all …]
104 int ddr_init(struct dram_timing_info *timing_info);105 int ddr_cfg_phy(struct dram_timing_info *timing_info);
85 timing_info = {} variable485 timing = timing_info.get(threaded_name)488 timing_info[threaded_name] = timing515 for threaded_name, timing in timing_info.items():
708 int ddr_init(struct dram_timing_info *timing_info);709 int ddr_cfg_phy(struct dram_timing_info *timing_info);
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