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Searched refs:timings (Results 1 – 25 of 130) sorted by relevance

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/u-boot/board/isee/igep00x0/
A Dspl.c20 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
24 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
25 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
26 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
29 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
30 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
31 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
42 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
43 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
47 timings->ctrla = NUMONYX_V_ACTIMA_200; in get_board_mem_timings()
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/u-boot/arch/arm/mach-imx/
A Dddrmc-vf610.c126 writel(DDRMC_CR12_WRLAT(timings->wrlat) | in ddrmc_ctrl_init_ddr3()
128 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | in ddrmc_ctrl_init_ddr3()
129 DDRMC_CR13_TCCD(timings->tccd) | in ddrmc_ctrl_init_ddr3()
132 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
133 DDRMC_CR14_TWTR(timings->twtr) | in ddrmc_ctrl_init_ddr3()
135 writel(DDRMC_CR16_TMRD(timings->tmrd) | in ddrmc_ctrl_init_ddr3()
153 writel(DDRMC_CR26_TREF(timings->tref) | in ddrmc_ctrl_init_ddr3()
159 writel(DDRMC_CR31_TXSNR(timings->txsnr) | in ddrmc_ctrl_init_ddr3()
162 writel(DDRMC_CR34_CKSRX(timings->cksrx) | in ddrmc_ctrl_init_ddr3()
173 writel(DDRMC_CR66_ZQCL(timings->zqcl) | in ddrmc_ctrl_init_ddr3()
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/u-boot/drivers/video/
A Dmxsfb.c157 timings->vsync_len.typ; in mxs_lcd_init()
169 writel(timings->vback_porch.typ + timings->vfront_porch.typ + in mxs_lcd_init()
170 timings->vsync_len.typ + timings->vactive.typ, in mxs_lcd_init()
173 (timings->hback_porch.typ + timings->hfront_porch.typ + in mxs_lcd_init()
174 timings->hsync_len.typ + timings->hactive.typ), in mxs_lcd_init()
176 writel(((timings->hback_porch.typ + timings->hsync_len.typ) << in mxs_lcd_init()
178 (timings->vback_porch.typ + timings->vsync_len.typ), in mxs_lcd_init()
205 mxs_lcd_init(dev, fb, timings, bpp); in mxs_probe_common()
296 struct display_timing timings; in mxs_video_probe() local
347 struct display_timing timings; in mxs_video_bind() local
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A Dmali_dp.c163 struct display_timing *timings) in malidp_setup_timings() argument
177 val = MALIDP_H_ACTIVE(timings->hactive.typ) | in malidp_setup_timings()
178 MALIDP_V_ACTIVE(timings->vactive.typ); in malidp_setup_timings()
187 struct display_timing *timings) in malidp_setup_mode() argument
194 malidp_setup_timings(malidp, timings); in malidp_setup_mode()
204 struct display_timing *timings, in malidp_setup_layer() argument
214 MALIDP_CMP_H_SIZE(timings->hactive.typ); in malidp_setup_layer()
219 MALIDP_IN_H_SIZE(timings->hactive.typ); in malidp_setup_layer()
240 struct display_timing *timings) in malidp_update_timings_from_edid() argument
267 struct display_timing timings; in malidp_probe() local
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A Ddw_mipi_dsi.c233 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ + in dsi_mode_vrefresh()
234 timings->hback_porch.typ + timings->hsync_len.typ; in dsi_mode_vrefresh()
235 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ + in dsi_mode_vrefresh()
236 timings->vback_porch.typ + timings->vsync_len.typ; in dsi_mode_vrefresh()
621 htotal = timings->hactive.typ + timings->hfront_porch.typ + in dw_mipi_dsi_line_timer_config()
622 timings->hback_porch.typ + timings->hsync_len.typ; in dw_mipi_dsi_line_timer_config()
624 hsa = timings->hsync_len.typ; in dw_mipi_dsi_line_timer_config()
625 hbp = timings->hback_porch.typ; in dw_mipi_dsi_line_timer_config()
646 vactive = timings->vactive.typ; in dw_mipi_dsi_vertical_timing_config()
647 vsa = timings->vsync_len.typ; in dw_mipi_dsi_vertical_timing_config()
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A Dsandbox_dsi_host.c20 struct display_timing *timings; member
27 struct display_timing *timings, in sandbox_dsi_host_init() argument
36 if (!timings) in sandbox_dsi_host_init()
51 priv->timings = timings; in sandbox_dsi_host_init()
64 ret = priv->phy_ops->get_lane_mbps(priv->device, priv->timings, 2, in sandbox_dsi_host_enable()
A Dmvebu_lcd.c533 struct display_timing timings; in mvebu_video_probe() local
543 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); in mvebu_video_probe()
551 lcd_info.x_res = timings.hactive.typ; in mvebu_video_probe()
552 lcd_info.x_fp = timings.hfront_porch.typ; in mvebu_video_probe()
553 lcd_info.x_bp = timings.hback_porch.typ; in mvebu_video_probe()
554 lcd_info.y_res = timings.vactive.typ; in mvebu_video_probe()
555 lcd_info.y_fp = timings.vfront_porch.typ; in mvebu_video_probe()
556 lcd_info.y_bp = timings.vback_porch.typ; in mvebu_video_probe()
A Ddsi-host-uclass.c16 struct display_timing *timings, in dsi_host_init() argument
25 return ops->init(dev, device, timings, max_data_lanes, phy_ops); in dsi_host_init()
A Dpanel-uclass.c42 struct display_timing *timings) in panel_get_display_timing() argument
49 return ops->get_display_timing(dev, timings); in panel_get_display_timing()
A Dtdo-tl070wsh30.c66 struct display_timing *timings) in tl070wsh30_panel_get_display_timing() argument
68 memcpy(timings, &default_timing, sizeof(*timings)); in tl070wsh30_panel_get_display_timing()
/u-boot/board/ti/beagle/
A Dbeagle.c157 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
163 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
164 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
170 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
171 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
177 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
178 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
187 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
188 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
201 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
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/u-boot/arch/arm/mach-omap2/omap3/
A Dsdrc.c103 struct board_sdrc_timings *timings) in write_sdrc_timings() argument
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
107 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
108 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
114 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
133 struct board_sdrc_timings timings; in do_sdrc_init() local
139 timings.sharing = SDRC_SHARING; in do_sdrc_init()
152 get_board_mem_timings(&timings); in do_sdrc_init()
162 writel(timings.sharing, &sdrc_base->sharing); in do_sdrc_init()
185 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
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/u-boot/board/logicpd/omap3som/
A Domap3logic.c79 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
81 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
86 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
87 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
88 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
89 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
92 timings->mcfg = MICRON_V_MCFG_165(256 << 20); in get_board_mem_timings()
93 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
94 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
95 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
/u-boot/drivers/mtd/nand/raw/
A Dnand_timings.c20 .timings.sdr = {
62 .timings.sdr = {
104 .timings.sdr = {
146 .timings.sdr = {
188 .timings.sdr = {
230 .timings.sdr = {
281 return &onfi_sdr_timings[mode].timings.sdr; in onfi_async_timing_mode_to_sdr_timings()
311 struct nand_sdr_timings *timings = &iface->timings.sdr; in onfi_init_data_interface() local
314 timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); in onfi_init_data_interface()
316 timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r); in onfi_init_data_interface()
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A Dsunxi_nand.c1246 min_clk_period = timings->tCS_min; in sunxi_nand_chip_set_timings()
1250 min_clk_period = timings->tCH_min; in sunxi_nand_chip_set_timings()
1254 min_clk_period = timings->tWP_min; in sunxi_nand_chip_set_timings()
1258 min_clk_period = timings->tWH_min; in sunxi_nand_chip_set_timings()
1266 min_clk_period = timings->tDS_min; in sunxi_nand_chip_set_timings()
1270 min_clk_period = timings->tDH_min; in sunxi_nand_chip_set_timings()
1282 min_clk_period = timings->tRP_min; in sunxi_nand_chip_set_timings()
1386 if (IS_ERR(timings)) in sunxi_nand_chip_init_timings()
1387 return PTR_ERR(timings); in sunxi_nand_chip_init_timings()
1676 if (IS_ERR(timings)) { in sunxi_nand_chip_init()
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A Docteontx_nand.c302 struct ndf_set_tm_par_cmd timings; member
608 set_timings(chip, &chip->timings, timings, sclk); in octeontx_nfc_chip_set_timings()
736 struct ndf_set_tm_par_cmd *timings) in ndf_queue_cmd_timing() argument
876 struct ndf_set_tm_par_cmd *timings; in ndf_build_pre_cmd() local
881 timings = &default_timing_parms; in ndf_build_pre_cmd()
886 timings = &octeontx_nand->timings; in ndf_build_pre_cmd()
893 rc = ndf_queue_cmd_timing(tn, timings); in ndf_build_pre_cmd()
2031 const struct nand_sdr_timings *timings; in octeontx_nfc_init() local
2053 if (IS_ERR(timings)) in octeontx_nfc_init()
2054 return PTR_ERR(timings); in octeontx_nfc_init()
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/u-boot/board/ti/omap3evm/
A Devm.c128 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
141 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
142 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
143 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
146 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
147 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
148 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
150 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
151 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/u-boot/drivers/video/stm32/
A Dstm32_ltdc.c373 struct display_timing *timings) in stm32_ltdc_set_mode() argument
381 hsync = timings->hsync_len.typ - 1; in stm32_ltdc_set_mode()
382 vsync = timings->vsync_len.typ - 1; in stm32_ltdc_set_mode()
504 struct display_timing timings; in stm32_ltdc_probe() local
559 0, &timings); in stm32_ltdc_probe()
569 timings.pixelclock.typ, rate); in stm32_ltdc_probe()
572 timings.pixelclock.typ, rate); in stm32_ltdc_probe()
603 priv->crop_w = timings.hactive.typ; in stm32_ltdc_probe()
604 priv->crop_h = timings.vactive.typ; in stm32_ltdc_probe()
608 timings.hactive.typ, timings.vactive.typ, in stm32_ltdc_probe()
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/u-boot/board/timll/devkit8000/
A Ddevkit8000.c197 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
200 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
201 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
204 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
205 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
207 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/u-boot/board/lg/sniper/
A Dsniper.c73 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
75 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
76 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
77 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
78 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
79 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/u-boot/test/dm/
A Ddsi_host.c27 struct display_timing *timings, in dm_test_dsi_host_phy_get_lane_mbps() argument
46 struct display_timing timings; in dm_test_dsi_host() local
51 ut_assertok(dsi_host_init(dev, &device, &timings, max_data_lanes, in dm_test_dsi_host()
/u-boot/arch/arm/dts/
A Delpida_ecb240abacn.dtsi24 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
25 compatible = "jedec,lpddr2-timings";
46 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
47 compatible = "jedec,lpddr2-timings";
/u-boot/arch/arm/mach-omap2/
A Demif-common.c621 const struct lpddr2_ac_timings *timings = 0; in get_timings_table() local
639 timings = device_timings[i]; in get_timings_table()
643 return timings; in get_timings_table()
714 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; in get_sdram_tim_1_reg()
736 val = max(min_tck->tCKE, timings->tCKE) - 1; in get_sdram_tim_2_reg()
746 val = ns_2_cycles(timings->tXSR) - 1; in get_sdram_tim_2_reg()
764 val = ns_2_cycles(timings->tRFCab) - 1; in get_sdram_tim_3_reg()
767 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; in get_sdram_tim_3_reg()
770 val = ns_2_cycles(timings->tZQCS) - 1; in get_sdram_tim_3_reg()
928 const struct lpddr2_ac_timings *timings; in emif_calculate_regs() local
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/u-boot/include/
A Ddsi_host.h26 struct display_timing *timings,
61 struct display_timing *timings,
/u-boot/drivers/core/
A Dofnode.c933 ofnode timings, node; in ofnode_decode_display_timing() local
938 if (!ofnode_valid(timings)) in ofnode_decode_display_timing()
942 ofnode_for_each_subnode(node, timings) { in ofnode_decode_display_timing()
997 ofnode timings; in ofnode_decode_panel_timing() local
1001 timings = ofnode_find_subnode(parent, "panel-timing"); in ofnode_decode_panel_timing()
1002 if (!ofnode_valid(timings)) in ofnode_decode_panel_timing()
1015 if (!ofnode_read_u32(timings, "vsync-active", &val)) { in ofnode_decode_panel_timing()
1023 if (!ofnode_read_u32(timings, "de-active", &val)) { in ofnode_decode_panel_timing()
1031 if (ofnode_read_bool(timings, "interlaced")) in ofnode_decode_panel_timing()
1033 if (ofnode_read_bool(timings, "doublescan")) in ofnode_decode_panel_timing()
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