| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_ddr3_1333.c | 58 u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */ in mctl_set_timing_params() local
91 if (tcl + 1 >= trtp + trp) in mctl_set_timing_params()
92 trtp = tcl + 2 - trp; in mctl_set_timing_params()
105 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
123 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | h6_lpddr3.c | 37 u8 trp = ns_to_t(18); in mctl_set_timing_params() local
93 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
111 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_params()
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| A D | ddr2_v3s.c | 19 u8 trp = ns_to_t(15); in mctl_set_timing_params() local
65 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
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| A D | ddr3_1333.c | 19 u8 trp = ns_to_t(15); in mctl_set_timing_params() local
68 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 19 u8 trp = max(ns_to_t(27), 2); in mctl_set_timing_params() local
64 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
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| A D | h616_ddr3_1333.c | 30 u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */ in mctl_set_timing_params() local
75 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, in mctl_set_timing_params()
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| /u-boot/board/work-microwave/work_92105/ |
| A D | work_92105_spl.c | 23 .trp = 52631578,
43 .trp = 52631578,
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| /u-boot/board/timll/devkit3250/ |
| A D | devkit3250_spl.c | 30 .trp = 83333333,
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| /u-boot/include/ |
| A D | spd.h | 42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ member
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| A D | ddr_spd.h | 42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ member
104 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ member
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| /u-boot/arch/m68k/include/asm/coldfire/ |
| A D | ata.h | 32 u8 trp; /* 0x0F */ member
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| /u-boot/arch/arm/dts/ |
| A D | rk3288-veyron-u-boot.dtsi | 24 rockchip,trp = <10>;
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 45 u32 trp; member
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| A D | sdram_rk3036.h | 46 u32 trp; member
243 u32 trp; member
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| A D | sdram_rk322x.h | 79 u32 trp; member
205 u32 trp; member
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| /u-boot/arch/arm/include/asm/arch-vf610/ |
| A D | ddrmc-vf610.h | 26 u8 trp; member
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| /u-boot/drivers/ram/ |
| A D | stm32_sdram.c | 131 u8 trp; member
204 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
214 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
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| /u-boot/arch/arm/mach-lpc32xx/ |
| A D | dram.c | 42 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
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| /u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| A D | emc.h | 84 u32 trp; member
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 51 rockchip,trp: tRP,AC timing parameters from the memory data-sheet
61 trp
143 rockchip,trp = <10>;
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| /u-boot/board/phytec/pcm052/ |
| A D | pcm052.c | 106 .trp = 6, in dram_init()
161 .trp = 6, in dram_init()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 103 u8 trp = ns_to_t(15); in auto_set_timing_para() local
154 trp = max(ns_to_t(27), 2); in auto_set_timing_para()
180 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 103 u8 trp = ns_to_t(15); in auto_set_timing_para() local
148 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | mem.h | 66 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ argument
70 ACTIM_CTRLA_TRP(trp) | \
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1287 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1393 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; in mx6_ddr3_cfg()
1395 trcd = trp; in mx6_ddr3_cfg()
1418 debug("trp=%d\n", trp); in mx6_ddr3_cfg()
1499 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | in mx6_ddr3_cfg()
1615 ((tcwl + twr + trp + trcd) in mx6_ddr3_cfg()
1617 ((trtp + trp + trcd - 4) in mx6_ddr3_cfg()
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