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/u-boot/arch/arm/include/asm/arch-tegra/
A Dpmc.h161 uint pmc_scratch45;
162 uint pmc_scratch46;
163 uint pmc_scratch47;
164 uint pmc_scratch48;
165 uint pmc_scratch49;
166 uint pmc_scratch50;
167 uint pmc_scratch51;
168 uint pmc_scratch52;
169 uint pmc_scratch53;
170 uint pmc_scratch54;
[all …]
A Ddc.h52 uint ctxsw; /* _CMD_CTXSW_0 */
137 uint h_pulse_ctrl;
151 uint v_pulse_ctrl;
158 uint v_pulse_ctrl;
160 uint v_pulse_pos_a;
346 uint rsvd_80c;
353 uint reserved0[0x2bc];
356 uint reserved1[0xd6];
359 uint reserved2[0x1b];
362 uint reserved3[0xd7];
[all …]
A Dusb.h13 uint id;
14 uint reserved0;
15 uint host;
16 uint device;
19 uint txbuf;
20 uint rxbuf;
43 uint usb_cmd;
44 uint usb_sts;
46 uint frindex;
73 uint otgsc;
[all …]
A Dclk_rst.h12 uint pll_base; /* the control register */
14 uint pll_out[2];
15 uint pll_misc; /* other misc things */
20 uint pll_base; /* the control register */
21 uint pll_misc; /* other misc things */
25 uint pllm_base; /* the control register */
26 uint pllm_out; /* output control */
27 uint pllm_misc1; /* misc1 */
28 uint pllm_misc2; /* misc2 */
33 uint set;
[all …]
A Duart.h12 uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
13 uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
14 uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
15 uint uart_lcr; /* UART_LCR_0, offset 0C */
16 uint uart_mcr; /* UART_MCR_0, offset 10 */
17 uint uart_lsr; /* UART_LSR_0, offset 14 */
18 uint uart_msr; /* UART_MSR_0, offset 18 */
19 uint uart_spr; /* UART_SPR_0, offset 1C */
20 uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
21 uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
[all …]
A Dscu.h12 uint scu_ctrl; /* SCU Control Register, offset 00 */
13 uint scu_cfg; /* SCU Config Register, offset 04 */
14 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
15 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
16 uint scu_reserved0[12]; /* reserved, offset 10-3C */
17 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
18 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
19 uint scu_reserved1[2]; /* reserved, offset 48-4C */
20 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
21 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
/u-boot/include/
A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
31 #define LCCR_BNUM_BIT ((uint)14)
33 #define LCCR_IEN_BIT ((uint)16)
36 #define LCCR_OEP_BIT ((uint)21)
37 #define LCCR_HSP_BIT ((uint)22)
38 #define LCCR_VSP_BIT ((uint)23)
39 #define LCCR_DP_BIT ((uint)24)
41 #define LCCR_LBW_BIT ((uint)27)
[all …]
A Dp2sb.h25 uint pid;
36 uint mmio_base;
79 uint pcr_read32(struct udevice *dev, uint offset);
80 uint pcr_read16(struct udevice *dev, uint offset);
81 uint pcr_read8(struct udevice *dev, uint offset);
92 void pcr_write32(struct udevice *dev, uint offset, uint data);
93 void pcr_write16(struct udevice *dev, uint offset, uint data);
94 void pcr_write8(struct udevice *dev, uint offset, uint data);
110 void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set);
111 void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set);
[all …]
A Dbitfield.h43 static inline uint bitfield_mask(uint shift, uint width) in bitfield_mask()
49 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract()
58 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace()
59 uint bitfield_val) in bitfield_replace()
61 uint mask = bitfield_mask(shift, width); in bitfield_replace()
67 static inline uint bitfield_shift(uint mask) in bitfield_shift()
73 static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) in bitfield_extract_by_mask()
75 uint shift = bitfield_shift(mask); in bitfield_extract_by_mask()
84 static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, in bitfield_replace_by_mask()
85 uint bitfield_val) in bitfield_replace_by_mask()
[all …]
A Dexpo.h65 uint scene_id;
66 uint next_id;
82 uint id;
102 uint id;
138 uint id;
171 uint str_id;
230 uint id;
231 uint key_id;
233 uint desc_id;
235 uint flags;
[all …]
A Dvideo_osd.h12 uint width;
14 uint height;
16 uint major_version;
18 uint minor_version;
83 int (*set_mem)(struct udevice *dev, uint col, uint row, u8 *buf,
84 size_t buflen, uint count);
95 int (*set_size)(struct udevice *dev, uint col, uint row);
113 int (*print)(struct udevice *dev, uint col, uint row, ulong color,
160 int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
172 int video_osd_set_size(struct udevice *dev, uint col, uint row);
[all …]
A Dpci_ep.h121 int (*set_bar)(struct udevice *dev, uint func_num,
132 int (*read_bar)(struct udevice *dev, uint func_num,
142 int (*clear_bar)(struct udevice *dev, uint func_num,
157 int (*map_addr)(struct udevice *dev, uint func_num,
182 int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
194 int (*get_msi)(struct udevice *dev, uint func_num);
207 int (*set_msix)(struct udevice *dev, uint func_num,
208 uint interrupts);
220 int (*get_msix)(struct udevice *dev, uint func_num);
342 int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
[all …]
A Dvideo_console.h94 int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch);
105 int (*move_rows)(struct udevice *dev, uint rowdst, uint rowsrc,
106 uint count);
118 int (*set_row)(struct udevice *dev, uint row, int clr);
170 const char *(*get_font_size)(struct udevice *dev, uint *sizep);
180 int (*select_font)(struct udevice *dev, const char *name, uint size);
205 int vidconsole_select_font(struct udevice *dev, const char *name, uint size);
219 int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch);
230 int vidconsole_move_rows(struct udevice *dev, uint rowdst, uint rowsrc,
231 uint count);
[all …]
A Dpwm.h30 int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
31 uint duty_ns);
41 int (*set_enable)(struct udevice *dev, uint channel, bool enable);
50 int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
68 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
69 uint duty_ns);
79 int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
89 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
/u-boot/arch/powerpc/include/asm/
A Dimmap_8xx.h18 uint sc_siumcr;
19 uint sc_sypcr;
20 uint sc_swt;
23 uint sc_sipend;
24 uint sc_simask;
25 uint sc_siel;
26 uint sc_sivec;
27 uint sc_tesr;
29 uint sc_sdcr;
59 uint pcmc_per;
[all …]
A Dcpm_8xx.h114 uint smc_idp; /* Internal */
119 uint smc_tdp; /* Internal */
165 uint scent_rstate;
166 uint scent_r_ptr;
169 uint scent_rtemp;
170 uint scent_tstate;
171 uint scent_t_ptr;
174 uint scent_ttemp;
324 uint scc_idp; /* Internal */
329 uint scc_tdp; /* Internal */
[all …]
A Dfsl_dma.h15 uint mr; /* DMA mode register */
31 uint sr; /* DMA status register */
38 uint sar; /* DMA source address register */
40 uint dar; /* DMA destination address register */
42 uint bcr; /* DMA byte count register */
49 uint mr; /* DMA mode register */
70 uint sr; /* DMA status register */
90 uint sar; /* DMA source address register */
103 uint bcr; /* DMA byte count register */
110 uint ssr; /* DMA source stride register */
[all …]
/u-boot/arch/arm/include/asm/arch-tegra30/
A Ddsi.h19 uint incr_syncpt; /* _INCR_SYNCPT_0 */
27 uint ctxsw; /* _CTXSW_0 */
28 uint dsi_rd_data; /* _DSI_RD_DATA_0 */
29 uint dsi_wr_data; /* _DSI_WR_DATA_0 */
31 uint int_enable; /* _INT_ENABLE_0 */
32 uint int_status; /* _INT_STATUS_0 */
33 uint int_mask; /* _INT_MASK_0 */
35 uint dsi_ctrl; /* _DSI_CONTROL_0 */
38 uint dsi_trigger; /* _DSI_TRIGGER_0 */
39 uint dsi_tx_crc; /* _DSI_TX_CRC_0 */
[all …]
A Dgpio.h20 uint gpio_config[TEGRA_GPIO_PORTS];
21 uint gpio_dir_out[TEGRA_GPIO_PORTS];
22 uint gpio_out[TEGRA_GPIO_PORTS];
23 uint gpio_in[TEGRA_GPIO_PORTS];
24 uint gpio_int_status[TEGRA_GPIO_PORTS];
25 uint gpio_int_enable[TEGRA_GPIO_PORTS];
26 uint gpio_int_level[TEGRA_GPIO_PORTS];
27 uint gpio_int_clear[TEGRA_GPIO_PORTS];
28 uint gpio_masked_config[TEGRA_GPIO_PORTS];
30 uint gpio_masked_out[TEGRA_GPIO_PORTS];
[all …]
/u-boot/arch/arm/include/asm/arch-tegra210/
A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29 uint gpio_masked_config[TEGRA_GPIO_PORTS];
31 uint gpio_masked_out[TEGRA_GPIO_PORTS];
[all …]
/u-boot/arch/arm/include/asm/arch-tegra124/
A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29 uint gpio_masked_config[TEGRA_GPIO_PORTS];
31 uint gpio_masked_out[TEGRA_GPIO_PORTS];
[all …]
/u-boot/include/acpi/
A Dacpigen.h111 uint ctype;
112 uint latency;
113 uint power;
132 uint percent;
133 uint power;
134 uint latency;
135 uint control;
136 uint status;
649 void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
856 uint first_core, uint core_count);
[all …]
/u-boot/drivers/bios_emulator/include/x86emu/
A Ddecode.h63 u8 fetch_data_byte (uint offset);
64 u8 fetch_data_byte_abs (uint segment, uint offset);
65 u16 fetch_data_word (uint offset);
66 u16 fetch_data_word_abs (uint segment, uint offset);
67 u32 fetch_data_long (uint offset);
68 u32 fetch_data_long_abs (uint segment, uint offset);
69 void store_data_byte (uint offset, u8 val);
70 void store_data_byte_abs (uint segment, uint offset, u8 val);
71 void store_data_word (uint offset, u16 val);
72 void store_data_word_abs (uint segment, uint offset, u16 val);
[all …]
/u-boot/drivers/misc/
A Dp2sb-uclass.c55 static inline void check_pcr_offset_align(uint offset, uint size) in check_pcr_offset_align()
62 uint pcr_read32(struct udevice *dev, uint offset) in pcr_read32()
65 uint val; in pcr_read32()
77 uint pcr_read16(struct udevice *dev, uint offset) in pcr_read16()
85 uint pcr_read8(struct udevice *dev, uint offset) in pcr_read8()
134 void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits32()
136 uint data32; in pcr_clrsetbits32()
144 void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits16()
146 uint data16; in pcr_clrsetbits16()
154 void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits8()
[all …]
/u-boot/arch/arm/include/asm/arch-tegra20/
A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];

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