/xen/xen/drivers/passthrough/amd/ |
A D | iommu_detect.c | 140 int rt = 0; in amd_iommu_detect_one_acpi() local 217 rt = get_iommu_capabilities(iommu->seg, bus, dev, func, in amd_iommu_detect_one_acpi() 219 if ( rt ) in amd_iommu_detect_one_acpi() 223 if ( rt ) in amd_iommu_detect_one_acpi() 227 rt = -ENOMEM; in amd_iommu_detect_one_acpi() 231 rt = pci_ro_device(iommu->seg, bus, PCI_DEVFN(dev, func)); in amd_iommu_detect_one_acpi() 232 if ( rt ) in amd_iommu_detect_one_acpi() 234 &PCI_SBDF(iommu->seg, iommu->bdf), rt); in amd_iommu_detect_one_acpi() 237 rt = 0; in amd_iommu_detect_one_acpi() 240 if ( rt ) in amd_iommu_detect_one_acpi() [all …]
|
/xen/xen/arch/arm/arm32/ |
A D | debug-scif.inc | 45 * rt: register which contains the character to transmit 47 .macro early_uart_transmit rb rt 48 strb \rt, [\rb, #TX_FIFO_REG] /* Write data register */ 49 ldrh \rt, [\rb, #STATUS_REG] /* Read status register */ 50 and \rt, \rt, #(~(SCFSR_TEND | SCFSR_TDFE)) /* Clear TEND and TDFE bits */ 51 strh \rt, [\rb, #STATUS_REG] /* Write status register */
|
A D | debug-8250.inc | 34 * rt: register which contains the character to transmit 36 .macro early_uart_transmit rb rt 37 str \rt, [\rb, #UART_THR] /* Write Transmit buffer */
|
A D | debug-exynos4210.inc | 36 * rt: register which contains the character to transmit 38 .macro early_uart_transmit rb rt 39 str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */
|
A D | debug-pl011.inc | 53 * rt: register which contains the character to transmit 55 .macro early_uart_transmit rb, rt 56 PL011_STRB \rt, [\rb, #DR] /* -> UARTDR (Data Register) */
|
/xen/xen/arch/arm/ |
A D | decode.c | 31 uint16_t rt; in decode_thumb2() local 36 rt = (hw2 >> 12) & 0xf; in decode_thumb2() 54 if ( rt == 15 ) in decode_thumb2() 62 update_dabt(dabt, rt, (hw1 >> 5) & 3, sign); in decode_thumb2() 100 if ( (opcode.ldr_str.rn == opcode.ldr_str.rt) && (opcode.ldr_str.rn != 31) ) in decode_arm64() 136 opcode.ldr_str.rt, opcode.ldr_str.size, opcode.ldr_str.imm9); in decode_arm64() 138 update_dabt(dabt, opcode.ldr_str.rt, opcode.ldr_str.size, false); in decode_arm64()
|
A D | decode.h | 39 unsigned int rt:5; /* Rt register */ member
|
/xen/xen/xsm/flask/ss/ |
A D | policydb.c | 659 struct range_trans *rt, *lrt = NULL; in policydb_destroy() local 705 for ( rt = p->range_tr; rt; rt = rt -> next ) in policydb_destroy() 713 lrt = rt; in policydb_destroy() 1750 struct range_trans *rt, *lrt; in policydb_read() local 2177 rt = xzalloc(struct range_trans); in policydb_read() 2178 if ( !rt ) in policydb_read() 2184 lrt->next = rt; in policydb_read() 2186 p->range_tr = rt; in policydb_read() 2190 rt->source_type = le32_to_cpu(buf[0]); in policydb_read() 2191 rt->target_type = le32_to_cpu(buf[1]); in policydb_read() [all …]
|
/xen/docs/features/ |
A D | sched_rtds.pandoc | 34 xl cpupool-create name=\"pool-rt\" sched=\"rtds\" cpus=[4,5,6,8] 38 * `xl sched-rtds -d vm-rt -v all` 39 * `xl sched-rtds -d vm-rt -v all -p 10000 -b 2500` 43 * `xl sched-rtds -d vm-rt -v 0 -p 20000 -b 10000 -e 1 -v 1 -p 45000 -b 12000 -e 0`
|
/xen/xen/common/sched/ |
A D | Makefile | 6 obj-$(CONFIG_SCHED_RTDS) += rt.o
|
/xen/xen/arch/arm/arm64/ |
A D | debug-imx-lpuart.inc | 37 * rt: register which contains the character to transmit
|
/xen/stubdom/vtpmmgr/ |
A D | tpm.h | 121 TPM_RESOURCE_TYPE rt //in
|
A D | tpm.c | 591 TPM_RESOURCE_TYPE rt) { in TPM_FlushSpecific() argument 598 PACK_IN(TPM_RESOURCE_TYPE, rt); in TPM_FlushSpecific()
|
/xen/xen/arch/x86/hvm/viridian/ |
A D | time.c | 25 const struct viridian_page *rt = &vd->reference_tsc; in update_reference_tsc() local 26 HV_REFERENCE_TSC_PAGE *p = rt->ptr; in update_reference_tsc()
|
/xen/tools/python/scripts/ |
A D | convert-legacy-stream | 108 def write_record(rt, *argl): argument 112 record = pack(libxc.RH_FORMAT, rt, length) + alldata
|
/xen/xen/arch/x86/mm/ |
A D | mem_sharing.c | 427 static void get_two_gfns(struct domain *rd, gfn_t rgfn, p2m_type_t *rt, in get_two_gfns() argument
|
/xen/ |
A D | MAINTAINERS | 490 F: xen/common/sched/rt.c
|
/xen/docs/man/ |
A D | xl.1.pod.in | 1178 This rt scheduler applies Preemptive Global Earliest Deadline First
|