1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dm9000.c: Version 1.2 12/15/2003
4 *
5 * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
6 * Copyright (C) 1997 Sten Wang
7 *
8 * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
9 *
10 * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
11 * 06/22/2001 Support DM9801 progrmming
12 * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
13 * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
14 * R17 = (R17 & 0xfff0) | NF + 3
15 * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
16 * R17 = (R17 & 0xfff0) | NF
17 *
18 * v1.00 modify by simon 2001.9.5
19 * change for kernel 2.4.x
20 *
21 * v1.1 11/09/2001 fix force mode bug
22 *
23 * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
24 * Fixed phy reset.
25 * Added tx/rx 32 bit mode.
26 * Cleaned up for kernel merge.
27 *
28 * --------------------------------------
29 *
30 * 12/15/2003 Initial port to u-boot by
31 * Sascha Hauer <saschahauer@web.de>
32 *
33 * 06/03/2008 Remy Bohmer <linux@bohmer.net>
34 * - Fixed the driver to work with DM9000A.
35 * (check on ISR receive status bit before reading the
36 * FIFO as described in DM9000 programming guide and
37 * application notes)
38 * - Added autodetect of databus width.
39 * - Made debug code compile again.
40 * - Adapt eth_send such that it matches the DM9000*
41 * application notes. Needed to make it work properly
42 * for DM9000A.
43 * - Adapted reset procedure to match DM9000 application
44 * notes (i.e. double reset)
45 * - some minor code cleanups
46 * These changes are tested with DM9000{A,EP,E} together
47 * with a 200MHz Atmel AT91SAM9261 core
48 *
49 * TODO: external MII is not functional, only internal at the moment.
50 */
51
52 #include <common.h>
53 #include <command.h>
54 #include <dm.h>
55 #include <malloc.h>
56 #include <net.h>
57 #include <asm/io.h>
58 #include <linux/delay.h>
59
60 #include "dm9000x.h"
61
62 /* Structure/enum declaration ------------------------------- */
63 struct dm9000_priv {
64 u32 runt_length_counter; /* counter: RX length < 64byte */
65 u32 long_length_counter; /* counter: RX length > 1514byte */
66 u32 reset_counter; /* counter: RESET */
67 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
68 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
69 u16 tx_pkt_cnt;
70 u16 queue_start_addr;
71 u16 dbug_cnt;
72 u8 phy_addr;
73 u8 device_wait_reset; /* device state */
74 unsigned char srom[128];
75 void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count);
76 void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count);
77 void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen);
78 void __iomem *base_io;
79 void __iomem *base_data;
80 };
81
82 /* DM9000 network board routine ---------------------------- */
83 #ifndef CONFIG_DM9000_BYTE_SWAPPED
84 #define dm9000_outb(d, r) writeb((d), (r))
85 #define dm9000_outw(d, r) writew((d), (r))
86 #define dm9000_outl(d, r) writel((d), (r))
87 #define dm9000_inb(r) readb(r)
88 #define dm9000_inw(r) readw(r)
89 #define dm9000_inl(r) readl(r)
90 #else
91 #define dm9000_outb(d, r) __raw_writeb(d, r)
92 #define dm9000_outw(d, r) __raw_writew(d, r)
93 #define dm9000_outl(d, r) __raw_writel(d, r)
94 #define dm9000_inb(r) __raw_readb(r)
95 #define dm9000_inw(r) __raw_readw(r)
96 #define dm9000_inl(r) __raw_readl(r)
97 #endif
98
99 #ifdef DEBUG
dm9000_dump_packet(const char * func,u8 * packet,int length)100 static void dm9000_dump_packet(const char *func, u8 *packet, int length)
101 {
102 int i;
103
104 printf("%s: length: %d\n", func, length);
105
106 for (i = 0; i < length; i++) {
107 if (i % 8 == 0)
108 printf("\n%s: %02x: ", func, i);
109 printf("%02x ", packet[i]);
110 }
111
112 printf("\n");
113 }
114 #else
dm9000_dump_packet(const char * func,u8 * packet,int length)115 static void dm9000_dump_packet(const char *func, u8 *packet, int length) {}
116 #endif
117
dm9000_outblk_8bit(struct dm9000_priv * db,void * data_ptr,int count)118 static void dm9000_outblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
119 {
120 int i;
121
122 for (i = 0; i < count; i++)
123 dm9000_outb((((u8 *)data_ptr)[i] & 0xff), db->base_data);
124 }
125
dm9000_outblk_16bit(struct dm9000_priv * db,void * data_ptr,int count)126 static void dm9000_outblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
127 {
128 int i;
129 u32 tmplen = (count + 1) / 2;
130
131 for (i = 0; i < tmplen; i++)
132 dm9000_outw(((u16 *)data_ptr)[i], db->base_data);
133 }
134
dm9000_outblk_32bit(struct dm9000_priv * db,void * data_ptr,int count)135 static void dm9000_outblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
136 {
137 int i;
138 u32 tmplen = (count + 3) / 4;
139
140 for (i = 0; i < tmplen; i++)
141 dm9000_outl(((u32 *)data_ptr)[i], db->base_data);
142 }
143
dm9000_inblk_8bit(struct dm9000_priv * db,void * data_ptr,int count)144 static void dm9000_inblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
145 {
146 int i;
147
148 for (i = 0; i < count; i++)
149 ((u8 *)data_ptr)[i] = dm9000_inb(db->base_data);
150 }
151
dm9000_inblk_16bit(struct dm9000_priv * db,void * data_ptr,int count)152 static void dm9000_inblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
153 {
154 int i;
155 u32 tmplen = (count + 1) / 2;
156
157 for (i = 0; i < tmplen; i++)
158 ((u16 *)data_ptr)[i] = dm9000_inw(db->base_data);
159 }
160
dm9000_inblk_32bit(struct dm9000_priv * db,void * data_ptr,int count)161 static void dm9000_inblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
162 {
163 int i;
164 u32 tmplen = (count + 3) / 4;
165
166 for (i = 0; i < tmplen; i++)
167 ((u32 *)data_ptr)[i] = dm9000_inl(db->base_data);
168 }
169
dm9000_rx_status_32bit(struct dm9000_priv * db,u16 * rxstatus,u16 * rxlen)170 static void dm9000_rx_status_32bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
171 {
172 u32 tmpdata;
173
174 dm9000_outb(DM9000_MRCMD, db->base_io);
175
176 tmpdata = dm9000_inl(db->base_data);
177 *rxstatus = __le16_to_cpu(tmpdata);
178 *rxlen = __le16_to_cpu(tmpdata >> 16);
179 }
180
dm9000_rx_status_16bit(struct dm9000_priv * db,u16 * rxstatus,u16 * rxlen)181 static void dm9000_rx_status_16bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
182 {
183 dm9000_outb(DM9000_MRCMD, db->base_io);
184
185 *rxstatus = __le16_to_cpu(dm9000_inw(db->base_data));
186 *rxlen = __le16_to_cpu(dm9000_inw(db->base_data));
187 }
188
dm9000_rx_status_8bit(struct dm9000_priv * db,u16 * rxstatus,u16 * rxlen)189 static void dm9000_rx_status_8bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
190 {
191 dm9000_outb(DM9000_MRCMD, db->base_io);
192
193 *rxstatus =
194 __le16_to_cpu(dm9000_inb(db->base_data) +
195 (dm9000_inb(db->base_data) << 8));
196 *rxlen =
197 __le16_to_cpu(dm9000_inb(db->base_data) +
198 (dm9000_inb(db->base_data) << 8));
199 }
200
201 /*
202 * Read a byte from I/O port
203 */
dm9000_ior(struct dm9000_priv * db,int reg)204 static u8 dm9000_ior(struct dm9000_priv *db, int reg)
205 {
206 dm9000_outb(reg, db->base_io);
207 return dm9000_inb(db->base_data);
208 }
209
210 /*
211 * Write a byte to I/O port
212 */
dm9000_iow(struct dm9000_priv * db,int reg,u8 value)213 static void dm9000_iow(struct dm9000_priv *db, int reg, u8 value)
214 {
215 dm9000_outb(reg, db->base_io);
216 dm9000_outb(value, db->base_data);
217 }
218
219 /*
220 * Read a word from phyxcer
221 */
dm9000_phy_read(struct dm9000_priv * db,int reg)222 static u16 dm9000_phy_read(struct dm9000_priv *db, int reg)
223 {
224 u16 val;
225
226 /* Fill the phyxcer register into REG_0C */
227 dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
228 dm9000_iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
229 udelay(100); /* Wait read complete */
230 dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
231 val = (dm9000_ior(db, DM9000_EPDRH) << 8) |
232 dm9000_ior(db, DM9000_EPDRL);
233
234 /* The read data keeps on REG_0D & REG_0E */
235 debug("%s(0x%x): 0x%x\n", __func__, reg, val);
236 return val;
237 }
238
239 /*
240 * Write a word to phyxcer
241 */
dm9000_phy_write(struct dm9000_priv * db,int reg,u16 value)242 static void dm9000_phy_write(struct dm9000_priv *db, int reg, u16 value)
243 {
244 /* Fill the phyxcer register into REG_0C */
245 dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
246
247 /* Fill the written data into REG_0D & REG_0E */
248 dm9000_iow(db, DM9000_EPDRL, (value & 0xff));
249 dm9000_iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
250 dm9000_iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
251 udelay(500); /* Wait write complete */
252 dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
253 debug("%s(reg:0x%x, value:0x%x)\n", __func__, reg, value);
254 }
255
256 /*
257 * Search DM9000 board, allocate space and register it
258 */
dm9000_probe(struct dm9000_priv * db)259 static int dm9000_probe(struct dm9000_priv *db)
260 {
261 u32 id_val;
262
263 id_val = dm9000_ior(db, DM9000_VIDL);
264 id_val |= dm9000_ior(db, DM9000_VIDH) << 8;
265 id_val |= dm9000_ior(db, DM9000_PIDL) << 16;
266 id_val |= dm9000_ior(db, DM9000_PIDH) << 24;
267 if (id_val != DM9000_ID) {
268 printf("dm9000 not found at 0x%p id: 0x%08x\n",
269 db->base_io, id_val);
270 return -1;
271 }
272
273 printf("dm9000 i/o: 0x%p, id: 0x%x\n", db->base_io, id_val);
274 return 0;
275 }
276
277 /* General Purpose dm9000 reset routine */
dm9000_reset(struct dm9000_priv * db)278 static void dm9000_reset(struct dm9000_priv *db)
279 {
280 debug("resetting DM9000\n");
281
282 /*
283 * Reset DM9000,
284 * see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
285 */
286
287 /* DEBUG: Make all GPIO0 outputs, all others inputs */
288 dm9000_iow(db, DM9000_GPCR, GPCR_GPIO0_OUT);
289 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
290 dm9000_iow(db, DM9000_GPR, 0);
291 /* Step 2: Software reset */
292 dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
293
294 do {
295 debug("resetting the DM9000, 1st reset\n");
296 udelay(25); /* Wait at least 20 us */
297 } while (dm9000_ior(db, DM9000_NCR) & 1);
298
299 dm9000_iow(db, DM9000_NCR, 0);
300 dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
301
302 do {
303 debug("resetting the DM9000, 2nd reset\n");
304 udelay(25); /* Wait at least 20 us */
305 } while (dm9000_ior(db, DM9000_NCR) & 1);
306
307 /* Check whether the ethernet controller is present */
308 if ((dm9000_ior(db, DM9000_PIDL) != 0x0) ||
309 (dm9000_ior(db, DM9000_PIDH) != 0x90))
310 printf("ERROR: resetting DM9000 -> not responding\n");
311 }
312
313 /* Initialize dm9000 board */
dm9000_init_common(struct dm9000_priv * db,u8 enetaddr[6])314 static int dm9000_init_common(struct dm9000_priv *db, u8 enetaddr[6])
315 {
316 int i, oft, lnk;
317 u8 io_mode;
318
319 /* RESET device */
320 dm9000_reset(db);
321
322 if (dm9000_probe(db) < 0)
323 return -1;
324
325 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
326 io_mode = dm9000_ior(db, DM9000_ISR) >> 6;
327
328 switch (io_mode) {
329 case 0x0: /* 16-bit mode */
330 printf("DM9000: running in 16 bit mode\n");
331 db->outblk = dm9000_outblk_16bit;
332 db->inblk = dm9000_inblk_16bit;
333 db->rx_status = dm9000_rx_status_16bit;
334 break;
335 case 0x01: /* 32-bit mode */
336 printf("DM9000: running in 32 bit mode\n");
337 db->outblk = dm9000_outblk_32bit;
338 db->inblk = dm9000_inblk_32bit;
339 db->rx_status = dm9000_rx_status_32bit;
340 break;
341 case 0x02: /* 8 bit mode */
342 printf("DM9000: running in 8 bit mode\n");
343 db->outblk = dm9000_outblk_8bit;
344 db->inblk = dm9000_inblk_8bit;
345 db->rx_status = dm9000_rx_status_8bit;
346 break;
347 default:
348 /* Assume 8 bit mode, will probably not work anyway */
349 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
350 db->outblk = dm9000_outblk_8bit;
351 db->inblk = dm9000_inblk_8bit;
352 db->rx_status = dm9000_rx_status_8bit;
353 break;
354 }
355
356 /* Program operating register, only internal phy supported */
357 dm9000_iow(db, DM9000_NCR, 0x0);
358 /* TX Polling clear */
359 dm9000_iow(db, DM9000_TCR, 0);
360 /* Less 3Kb, 200us */
361 dm9000_iow(db, DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
362 /* Flow Control : High/Low Water */
363 dm9000_iow(db, DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
364 /* SH FIXME: This looks strange! Flow Control */
365 dm9000_iow(db, DM9000_FCR, 0x0);
366 /* Special Mode */
367 dm9000_iow(db, DM9000_SMCR, 0);
368 /* clear TX status */
369 dm9000_iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
370 /* Clear interrupt status */
371 dm9000_iow(db, DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
372
373 printf("MAC: %pM\n", enetaddr);
374 if (!is_valid_ethaddr(enetaddr))
375 printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
376
377 /* fill device MAC address registers */
378 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
379 dm9000_iow(db, oft, enetaddr[i]);
380 for (i = 0, oft = 0x16; i < 8; i++, oft++)
381 dm9000_iow(db, oft, 0xff);
382
383 /* read back mac, just to be sure */
384 for (i = 0, oft = 0x10; i < 6; i++, oft++)
385 debug("%02x:", dm9000_ior(db, oft));
386 debug("\n");
387
388 /* Activate DM9000 */
389 /* RX enable */
390 dm9000_iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
391 /* Enable TX/RX interrupt mask */
392 dm9000_iow(db, DM9000_IMR, IMR_PAR);
393
394 i = 0;
395 while (!(dm9000_phy_read(db, 1) & 0x20)) { /* autonegation complete bit */
396 udelay(1000);
397 i++;
398 if (i == 10000) {
399 printf("could not establish link\n");
400 return 0;
401 }
402 }
403
404 /* see what we've got */
405 lnk = dm9000_phy_read(db, 17) >> 12;
406 printf("operating at ");
407 switch (lnk) {
408 case 1:
409 printf("10M half duplex ");
410 break;
411 case 2:
412 printf("10M full duplex ");
413 break;
414 case 4:
415 printf("100M half duplex ");
416 break;
417 case 8:
418 printf("100M full duplex ");
419 break;
420 default:
421 printf("unknown: %d ", lnk);
422 break;
423 }
424 printf("mode\n");
425 return 0;
426 }
427
428 /*
429 * Hardware start transmission.
430 * Send a packet to media from the upper layer.
431 */
dm9000_send_common(struct dm9000_priv * db,void * packet,int length)432 static int dm9000_send_common(struct dm9000_priv *db, void *packet, int length)
433 {
434 int tmo;
435
436 dm9000_dump_packet(__func__, packet, length);
437
438 dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
439
440 /* Move data to DM9000 TX RAM */
441 dm9000_outb(DM9000_MWCMD, db->base_io); /* Prepare for TX-data */
442
443 /* push the data to the TX-fifo */
444 db->outblk(db, packet, length);
445
446 /* Set TX length to DM9000 */
447 dm9000_iow(db, DM9000_TXPLL, length & 0xff);
448 dm9000_iow(db, DM9000_TXPLH, (length >> 8) & 0xff);
449
450 /* Issue TX polling command */
451 dm9000_iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
452
453 /* wait for end of transmission */
454 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
455 while (!(dm9000_ior(db, DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
456 !(dm9000_ior(db, DM9000_ISR) & IMR_PTM)) {
457 if (get_timer(0) >= tmo) {
458 printf("transmission timeout\n");
459 break;
460 }
461 }
462 dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
463
464 debug("transmit done\n\n");
465 return 0;
466 }
467
468 /*
469 * Stop the interface.
470 * The interface is stopped when it is brought.
471 */
dm9000_halt_common(struct dm9000_priv * db)472 static void dm9000_halt_common(struct dm9000_priv *db)
473 {
474 /* RESET device */
475 dm9000_phy_write(db, 0, 0x8000); /* PHY RESET */
476 dm9000_iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
477 dm9000_iow(db, DM9000_IMR, 0x80); /* Disable all interrupt */
478 dm9000_iow(db, DM9000_RCR, 0x00); /* Disable RX */
479 }
480
481 /*
482 * Received a packet and pass to upper layer
483 */
dm9000_recv_common(struct dm9000_priv * db,uchar * rdptr)484 static int dm9000_recv_common(struct dm9000_priv *db, uchar *rdptr)
485 {
486 u8 rxbyte;
487 u16 rxstatus, rxlen = 0;
488
489 /*
490 * Check packet ready or not, we must check
491 * the ISR status first for DM9000A
492 */
493 if (!(dm9000_ior(db, DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
494 return 0;
495
496 dm9000_iow(db, DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
497
498 /* There is _at least_ 1 package in the fifo, read them all */
499 dm9000_ior(db, DM9000_MRCMDX); /* Dummy read */
500
501 /*
502 * Get most updated data,
503 * only look at bits 0:1, See application notes DM9000
504 */
505 rxbyte = dm9000_inb(db->base_data) & 0x03;
506
507 /* Status check: this byte must be 0 or 1 */
508 if (rxbyte > DM9000_PKT_RDY) {
509 dm9000_iow(db, DM9000_RCR, 0x00); /* Stop Device */
510 dm9000_iow(db, DM9000_ISR, 0x80); /* Stop INT request */
511 printf("DM9000 error: status check fail: 0x%x\n",
512 rxbyte);
513 return -EINVAL;
514 }
515
516 if (rxbyte != DM9000_PKT_RDY)
517 return 0; /* No packet received, ignore */
518
519 debug("receiving packet\n");
520
521 /* A packet ready now & Get status/length */
522 db->rx_status(db, &rxstatus, &rxlen);
523
524 debug("rx status: 0x%04x rx len: %d\n", rxstatus, rxlen);
525
526 /* Move data from DM9000 */
527 /* Read received packet from RX SRAM */
528 db->inblk(db, rdptr, rxlen);
529
530 if (rxstatus & 0xbf00 || rxlen < 0x40 || rxlen > DM9000_PKT_MAX) {
531 if (rxstatus & 0x100)
532 printf("rx fifo error\n");
533 if (rxstatus & 0x200)
534 printf("rx crc error\n");
535 if (rxstatus & 0x8000)
536 printf("rx length error\n");
537 if (rxlen > DM9000_PKT_MAX) {
538 printf("rx length too big\n");
539 dm9000_reset(db);
540 }
541 return -EINVAL;
542 }
543
544 return rxlen;
545 }
546
547 /*
548 * Read a word data from SROM
549 */
550 #if !defined(CONFIG_DM9000_NO_SROM)
dm9000_read_srom_word(struct dm9000_priv * db,int offset,u8 * to)551 static void dm9000_read_srom_word(struct dm9000_priv *db, int offset, u8 *to)
552 {
553 dm9000_iow(db, DM9000_EPAR, offset);
554 dm9000_iow(db, DM9000_EPCR, 0x4);
555 mdelay(8);
556 dm9000_iow(db, DM9000_EPCR, 0x0);
557 to[0] = dm9000_ior(db, DM9000_EPDRL);
558 to[1] = dm9000_ior(db, DM9000_EPDRH);
559 }
560
dm9000_get_enetaddr(struct dm9000_priv * db,u8 * enetaddr)561 static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr)
562 {
563 int i;
564
565 for (i = 0; i < 3; i++)
566 dm9000_read_srom_word(db, i, enetaddr + (2 * i));
567 }
568 #else
dm9000_get_enetaddr(struct dm9000_priv * db,u8 * enetaddr)569 static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {}
570 #endif
571
dm9000_start(struct udevice * dev)572 static int dm9000_start(struct udevice *dev)
573 {
574 struct dm9000_priv *db = dev_get_priv(dev);
575 struct eth_pdata *pdata = dev_get_plat(dev);
576
577 return dm9000_init_common(db, pdata->enetaddr);
578 }
579
dm9000_stop(struct udevice * dev)580 static void dm9000_stop(struct udevice *dev)
581 {
582 struct dm9000_priv *db = dev_get_priv(dev);
583
584 dm9000_halt_common(db);
585 }
586
dm9000_send(struct udevice * dev,void * packet,int length)587 static int dm9000_send(struct udevice *dev, void *packet, int length)
588 {
589 struct dm9000_priv *db = dev_get_priv(dev);
590 int ret;
591
592 ret = dm9000_send_common(db, packet, length);
593
594 return ret ? 0 : -ETIMEDOUT;
595 }
596
dm9000_recv(struct udevice * dev,int flags,uchar ** packetp)597 static int dm9000_recv(struct udevice *dev, int flags, uchar **packetp)
598 {
599 struct dm9000_priv *db = dev_get_priv(dev);
600 uchar *data = net_rx_packets[0];
601 int ret;
602
603 ret = dm9000_recv_common(db, data);
604 if (ret > 0)
605 *packetp = (void *)data;
606
607 return ret >= 0 ? ret : -EAGAIN;
608 }
609
dm9000_write_hwaddr(struct udevice * dev)610 static int dm9000_write_hwaddr(struct udevice *dev)
611 {
612 struct dm9000_priv *db = dev_get_priv(dev);
613 struct eth_pdata *pdata = dev_get_plat(dev);
614 int i, oft;
615
616 /* fill device MAC address registers */
617 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
618 dm9000_iow(db, oft, pdata->enetaddr[i]);
619
620 for (i = 0, oft = 0x16; i < 8; i++, oft++)
621 dm9000_iow(db, oft, 0xff);
622
623 /* read back mac, just to be sure */
624 for (i = 0, oft = 0x10; i < 6; i++, oft++)
625 debug("%02x:", dm9000_ior(db, oft));
626
627 debug("\n");
628
629 return 0;
630 }
631
dm9000_read_rom_hwaddr(struct udevice * dev)632 static int dm9000_read_rom_hwaddr(struct udevice *dev)
633 {
634 struct dm9000_priv *db = dev_get_priv(dev);
635 struct eth_pdata *pdata = dev_get_plat(dev);
636
637 dm9000_get_enetaddr(db, pdata->enetaddr);
638
639 return !is_valid_ethaddr(pdata->enetaddr);
640 }
641
dm9000_bind(struct udevice * dev)642 static int dm9000_bind(struct udevice *dev)
643 {
644 return device_set_name(dev, dev->name);
645 }
646
dm9000_of_to_plat(struct udevice * dev)647 static int dm9000_of_to_plat(struct udevice *dev)
648 {
649 struct dm9000_priv *db = dev_get_priv(dev);
650 struct eth_pdata *pdata = dev_get_plat(dev);
651
652 pdata->iobase = dev_read_addr_index(dev, 0);
653 db->base_io = (void __iomem *)pdata->iobase;
654 db->base_data = dev_read_addr_index_ptr(dev, 1);
655
656 return 0;
657 }
658
659 static const struct eth_ops dm9000_ops = {
660 .start = dm9000_start,
661 .stop = dm9000_stop,
662 .send = dm9000_send,
663 .recv = dm9000_recv,
664 .write_hwaddr = dm9000_write_hwaddr,
665 .read_rom_hwaddr = dm9000_read_rom_hwaddr,
666 };
667
668 static const struct udevice_id dm9000_ids[] = {
669 { .compatible = "davicom,dm9000" },
670 { }
671 };
672
673 U_BOOT_DRIVER(dm9000) = {
674 .name = "eth_dm9000",
675 .id = UCLASS_ETH,
676 .of_match = dm9000_ids,
677 .bind = dm9000_bind,
678 .of_to_plat = dm9000_of_to_plat,
679 .ops = &dm9000_ops,
680 .priv_auto = sizeof(struct dm9000_priv),
681 .plat_auto = sizeof(struct eth_pdata),
682 .flags = DM_FLAG_ALLOC_PRIV_DMA,
683 };
684