1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * bcm2835 sdhost driver.
4 *
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
8 *
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
13 * support.
14 *
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
19 *
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
25 * which is based on
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
31 */
32 #include <clk.h>
33 #include <common.h>
34 #include <dm.h>
35 #include <mmc.h>
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <dm/device_compat.h>
40 #include <linux/bitops.h>
41 #include <linux/bug.h>
42 #include <linux/compat.h>
43 #include <linux/delay.h>
44 #include <linux/io.h>
45 #include <linux/iopoll.h>
46 #include <linux/sizes.h>
47 #include <mach/gpio.h>
48 #include <power/regulator.h>
49
50 #define msleep(a) udelay(a * 1000)
51
52 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
53 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
54 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
55 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
56 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
57 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
58 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
59 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
60 #define SDHSTS 0x20 /* SD host status - 11 R/W */
61 #define SDVDD 0x30 /* SD card power control - 1 R/W */
62 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
63 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
64 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
65 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
66 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
67
68 #define SDCMD_NEW_FLAG 0x8000
69 #define SDCMD_FAIL_FLAG 0x4000
70 #define SDCMD_BUSYWAIT 0x800
71 #define SDCMD_NO_RESPONSE 0x400
72 #define SDCMD_LONG_RESPONSE 0x200
73 #define SDCMD_WRITE_CMD 0x80
74 #define SDCMD_READ_CMD 0x40
75 #define SDCMD_CMD_MASK 0x3f
76
77 #define SDCDIV_MAX_CDIV 0x7ff
78
79 #define SDHSTS_BUSY_IRPT 0x400
80 #define SDHSTS_BLOCK_IRPT 0x200
81 #define SDHSTS_SDIO_IRPT 0x100
82 #define SDHSTS_REW_TIME_OUT 0x80
83 #define SDHSTS_CMD_TIME_OUT 0x40
84 #define SDHSTS_CRC16_ERROR 0x20
85 #define SDHSTS_CRC7_ERROR 0x10
86 #define SDHSTS_FIFO_ERROR 0x08
87 #define SDHSTS_DATA_FLAG 0x01
88
89 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
90 SDHSTS_BLOCK_IRPT | \
91 SDHSTS_SDIO_IRPT | \
92 SDHSTS_REW_TIME_OUT | \
93 SDHSTS_CMD_TIME_OUT | \
94 SDHSTS_CRC16_ERROR | \
95 SDHSTS_CRC7_ERROR | \
96 SDHSTS_FIFO_ERROR)
97
98 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
99 SDHSTS_CRC16_ERROR | \
100 SDHSTS_REW_TIME_OUT | \
101 SDHSTS_FIFO_ERROR)
102
103 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
104 SDHSTS_TRANSFER_ERROR_MASK)
105
106 #define SDHCFG_BUSY_IRPT_EN BIT(10)
107 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
108 #define SDHCFG_SDIO_IRPT_EN BIT(5)
109 #define SDHCFG_DATA_IRPT_EN BIT(4)
110 #define SDHCFG_SLOW_CARD BIT(3)
111 #define SDHCFG_WIDE_EXT_BUS BIT(2)
112 #define SDHCFG_WIDE_INT_BUS BIT(1)
113 #define SDHCFG_REL_CMD_LINE BIT(0)
114
115 #define SDVDD_POWER_OFF 0
116 #define SDVDD_POWER_ON 1
117
118 #define SDEDM_FORCE_DATA_MODE BIT(19)
119 #define SDEDM_CLOCK_PULSE BIT(20)
120 #define SDEDM_BYPASS BIT(21)
121
122 #define SDEDM_FIFO_FILL_SHIFT 4
123 #define SDEDM_FIFO_FILL_MASK 0x1f
edm_fifo_fill(u32 edm)124 static u32 edm_fifo_fill(u32 edm)
125 {
126 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
127 }
128
129 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
130 #define SDEDM_READ_THRESHOLD_SHIFT 14
131 #define SDEDM_THRESHOLD_MASK 0x1f
132
133 #define SDEDM_FSM_MASK 0xf
134 #define SDEDM_FSM_IDENTMODE 0x0
135 #define SDEDM_FSM_DATAMODE 0x1
136 #define SDEDM_FSM_READDATA 0x2
137 #define SDEDM_FSM_WRITEDATA 0x3
138 #define SDEDM_FSM_READWAIT 0x4
139 #define SDEDM_FSM_READCRC 0x5
140 #define SDEDM_FSM_WRITECRC 0x6
141 #define SDEDM_FSM_WRITEWAIT1 0x7
142 #define SDEDM_FSM_POWERDOWN 0x8
143 #define SDEDM_FSM_POWERUP 0x9
144 #define SDEDM_FSM_WRITESTART1 0xa
145 #define SDEDM_FSM_WRITESTART2 0xb
146 #define SDEDM_FSM_GENPULSES 0xc
147 #define SDEDM_FSM_WRITEWAIT2 0xd
148 #define SDEDM_FSM_STARTPOWDOWN 0xf
149
150 #define SDDATA_FIFO_WORDS 16
151
152 #define FIFO_READ_THRESHOLD 4
153 #define FIFO_WRITE_THRESHOLD 4
154 #define SDDATA_FIFO_PIO_BURST 8
155
156 #define SDHST_TIMEOUT_MAX_USEC 100000
157
158 struct bcm2835_plat {
159 struct mmc_config cfg;
160 struct mmc mmc;
161 };
162
163 struct bcm2835_host {
164 void __iomem *ioaddr;
165 u32 phys_addr;
166
167 int clock; /* Current clock speed */
168 unsigned int max_clk; /* Max possible freq */
169 unsigned int blocks; /* remaining PIO blocks */
170
171 u32 ns_per_fifo_word;
172
173 /* cached registers */
174 u32 hcfg;
175 u32 cdiv;
176
177 struct mmc_cmd *cmd; /* Current command */
178 struct mmc_data *data; /* Current data request */
179 bool use_busy:1; /* Wait for busy interrupt */
180
181 struct udevice *dev;
182 struct mmc *mmc;
183 struct bcm2835_plat *plat;
184 unsigned int firmware_sets_cdiv:1;
185 };
186
bcm2835_dumpregs(struct bcm2835_host * host)187 static void bcm2835_dumpregs(struct bcm2835_host *host)
188 {
189 dev_dbg(host->dev, "=========== REGISTER DUMP ===========\n");
190 dev_dbg(host->dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
191 dev_dbg(host->dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
192 dev_dbg(host->dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
193 dev_dbg(host->dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
194 dev_dbg(host->dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
195 dev_dbg(host->dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
196 dev_dbg(host->dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
197 dev_dbg(host->dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
198 dev_dbg(host->dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
199 dev_dbg(host->dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
200 dev_dbg(host->dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
201 dev_dbg(host->dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
202 dev_dbg(host->dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
203 dev_dbg(host->dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
204 dev_dbg(host->dev, "===========================================\n");
205 }
206
bcm2835_reset_internal(struct bcm2835_host * host)207 static void bcm2835_reset_internal(struct bcm2835_host *host)
208 {
209 u32 temp;
210
211 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
212 writel(0, host->ioaddr + SDCMD);
213 writel(0, host->ioaddr + SDARG);
214 /* Set timeout to a big enough value so we don't hit it */
215 writel(0xf00000, host->ioaddr + SDTOUT);
216 writel(0, host->ioaddr + SDCDIV);
217 /* Clear status register */
218 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
219 writel(0, host->ioaddr + SDHCFG);
220 writel(0, host->ioaddr + SDHBCT);
221 writel(0, host->ioaddr + SDHBLC);
222
223 /* Limit fifo usage due to silicon bug */
224 temp = readl(host->ioaddr + SDEDM);
225 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
226 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
227 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
228 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
229 writel(temp, host->ioaddr + SDEDM);
230 /* Wait for FIFO threshold to populate */
231 msleep(20);
232 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
233 /* Wait for all components to go through power on cycle */
234 msleep(20);
235 host->clock = 0;
236 writel(host->hcfg, host->ioaddr + SDHCFG);
237 writel(SDCDIV_MAX_CDIV, host->ioaddr + SDCDIV);
238 }
239
bcm2835_wait_transfer_complete(struct bcm2835_host * host)240 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
241 {
242 ulong tstart_ms = get_timer(0);
243
244 while (1) {
245 u32 edm, fsm;
246
247 edm = readl(host->ioaddr + SDEDM);
248 fsm = edm & SDEDM_FSM_MASK;
249
250 if ((fsm == SDEDM_FSM_IDENTMODE) ||
251 (fsm == SDEDM_FSM_DATAMODE))
252 break;
253
254 if ((fsm == SDEDM_FSM_READWAIT) ||
255 (fsm == SDEDM_FSM_WRITESTART1) ||
256 (fsm == SDEDM_FSM_READDATA)) {
257 writel(edm | SDEDM_FORCE_DATA_MODE,
258 host->ioaddr + SDEDM);
259 break;
260 }
261
262 /* Error out after ~1s */
263 ulong tlapse_ms = get_timer(tstart_ms);
264 if ( tlapse_ms > 1000 /* ms */ ) {
265
266 dev_err(host->dev,
267 "wait_transfer_complete - still waiting after %lu ms\n",
268 tlapse_ms);
269 bcm2835_dumpregs(host);
270 return -ETIMEDOUT;
271 }
272 }
273
274 return 0;
275 }
276
bcm2835_transfer_block_pio(struct bcm2835_host * host,bool is_read)277 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
278 {
279 struct mmc_data *data = host->data;
280 size_t blksize = data->blocksize;
281 int copy_words;
282 u32 hsts = 0;
283 u32 *buf;
284
285 if (blksize % sizeof(u32))
286 return -EINVAL;
287
288 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
289
290 if (is_read)
291 data->dest += blksize;
292 else
293 data->src += blksize;
294
295 copy_words = blksize / sizeof(u32);
296
297 /*
298 * Copy all contents from/to the FIFO as far as it reaches,
299 * then wait for it to fill/empty again and rewind.
300 */
301 while (copy_words) {
302 int burst_words, words;
303 u32 edm;
304
305 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
306 edm = readl(host->ioaddr + SDEDM);
307 if (is_read)
308 words = edm_fifo_fill(edm);
309 else
310 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
311
312 if (words < burst_words) {
313 int fsm_state = (edm & SDEDM_FSM_MASK);
314
315 if ((is_read &&
316 (fsm_state != SDEDM_FSM_READDATA &&
317 fsm_state != SDEDM_FSM_READWAIT &&
318 fsm_state != SDEDM_FSM_READCRC)) ||
319 (!is_read &&
320 (fsm_state != SDEDM_FSM_WRITEDATA &&
321 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
322 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
323 fsm_state != SDEDM_FSM_WRITECRC &&
324 fsm_state != SDEDM_FSM_WRITESTART1 &&
325 fsm_state != SDEDM_FSM_WRITESTART2))) {
326 hsts = readl(host->ioaddr + SDHSTS);
327 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
328 if (hsts & SDHSTS_ERROR_MASK)
329 break;
330 }
331
332 continue;
333 } else if (words > copy_words) {
334 words = copy_words;
335 }
336
337 copy_words -= words;
338
339 /* Copy current chunk to/from the FIFO */
340 while (words) {
341 if (is_read)
342 *(buf++) = readl(host->ioaddr + SDDATA);
343 else
344 writel(*(buf++), host->ioaddr + SDDATA);
345 words--;
346 }
347 }
348
349 return 0;
350 }
351
bcm2835_transfer_pio(struct bcm2835_host * host)352 static int bcm2835_transfer_pio(struct bcm2835_host *host)
353 {
354 u32 sdhsts;
355 bool is_read;
356 int ret = 0;
357
358 is_read = (host->data->flags & MMC_DATA_READ) != 0;
359 ret = bcm2835_transfer_block_pio(host, is_read);
360 if (ret)
361 return ret;
362
363 sdhsts = readl(host->ioaddr + SDHSTS);
364 if (sdhsts & (SDHSTS_CRC16_ERROR |
365 SDHSTS_CRC7_ERROR |
366 SDHSTS_FIFO_ERROR)) {
367 printf("%s transfer error - HSTS %08x\n",
368 is_read ? "read" : "write", sdhsts);
369 ret = -EILSEQ;
370 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
371 SDHSTS_REW_TIME_OUT))) {
372 printf("%s timeout error - HSTS %08x\n",
373 is_read ? "read" : "write", sdhsts);
374 ret = -ETIMEDOUT;
375 }
376
377 return ret;
378 }
379
bcm2835_prepare_data(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)380 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
381 struct mmc_data *data)
382 {
383 WARN_ON(host->data);
384
385 host->data = data;
386 if (!data)
387 return;
388
389 /* Use PIO */
390 host->blocks = data->blocks;
391
392 writel(data->blocksize, host->ioaddr + SDHBCT);
393 writel(data->blocks, host->ioaddr + SDHBLC);
394 }
395
bcm2835_read_wait_sdcmd(struct bcm2835_host * host)396 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
397 {
398 u32 value;
399 int ret;
400 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
401
402 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
403 !(value & SDCMD_NEW_FLAG), timeout_us);
404 if (ret == -ETIMEDOUT)
405 printf("%s: timeout (%d us)\n", __func__, timeout_us);
406
407 return value;
408 }
409
bcm2835_send_command(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)410 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
411 struct mmc_data *data)
412 {
413 u32 sdcmd, sdhsts;
414
415 WARN_ON(host->cmd);
416
417 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
418 printf("unsupported response type!\n");
419 return -EINVAL;
420 }
421
422 sdcmd = bcm2835_read_wait_sdcmd(host);
423 if (sdcmd & SDCMD_NEW_FLAG) {
424 printf("previous command never completed.\n");
425 bcm2835_dumpregs(host);
426 return -EBUSY;
427 }
428
429 host->cmd = cmd;
430
431 /* Clear any error flags */
432 sdhsts = readl(host->ioaddr + SDHSTS);
433 if (sdhsts & SDHSTS_ERROR_MASK)
434 writel(sdhsts, host->ioaddr + SDHSTS);
435
436 bcm2835_prepare_data(host, cmd, data);
437
438 writel(cmd->cmdarg, host->ioaddr + SDARG);
439
440 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
441
442 host->use_busy = false;
443 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
444 sdcmd |= SDCMD_NO_RESPONSE;
445 } else {
446 if (cmd->resp_type & MMC_RSP_136)
447 sdcmd |= SDCMD_LONG_RESPONSE;
448 if (cmd->resp_type & MMC_RSP_BUSY) {
449 sdcmd |= SDCMD_BUSYWAIT;
450 host->use_busy = true;
451 }
452 }
453
454 if (data) {
455 if (data->flags & MMC_DATA_WRITE)
456 sdcmd |= SDCMD_WRITE_CMD;
457 if (data->flags & MMC_DATA_READ)
458 sdcmd |= SDCMD_READ_CMD;
459 }
460
461 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
462
463 return 0;
464 }
465
bcm2835_finish_command(struct bcm2835_host * host)466 static int bcm2835_finish_command(struct bcm2835_host *host)
467 {
468 struct mmc_cmd *cmd = host->cmd;
469 u32 sdcmd;
470 int ret = 0;
471
472 sdcmd = bcm2835_read_wait_sdcmd(host);
473
474 /* Check for errors */
475 if (sdcmd & SDCMD_NEW_FLAG) {
476 printf("command never completed.\n");
477 bcm2835_dumpregs(host);
478 return -EIO;
479 } else if (sdcmd & SDCMD_FAIL_FLAG) {
480 u32 sdhsts = readl(host->ioaddr + SDHSTS);
481
482 /* Clear the errors */
483 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
484
485 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
486 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
487 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
488 ret = -ETIMEDOUT;
489 } else {
490 printf("unexpected command %d error\n",
491 host->cmd->cmdidx);
492 bcm2835_dumpregs(host);
493 ret = -EILSEQ;
494 }
495
496 return ret;
497 }
498 }
499
500 if (cmd->resp_type & MMC_RSP_PRESENT) {
501 if (cmd->resp_type & MMC_RSP_136) {
502 int i;
503
504 for (i = 0; i < 4; i++) {
505 cmd->response[3 - i] =
506 readl(host->ioaddr + SDRSP0 + i * 4);
507 }
508 } else {
509 cmd->response[0] = readl(host->ioaddr + SDRSP0);
510 }
511 }
512
513 /* Processed actual command. */
514 host->cmd = NULL;
515
516 return ret;
517 }
518
bcm2835_check_cmd_error(struct bcm2835_host * host,u32 intmask)519 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
520 {
521 int ret = -EINVAL;
522
523 if (!(intmask & SDHSTS_ERROR_MASK))
524 return 0;
525
526 if (!host->cmd)
527 return -EINVAL;
528
529 printf("sdhost_busy_irq: intmask %08x\n", intmask);
530 if (intmask & SDHSTS_CRC7_ERROR) {
531 ret = -EILSEQ;
532 } else if (intmask & (SDHSTS_CRC16_ERROR |
533 SDHSTS_FIFO_ERROR)) {
534 ret = -EILSEQ;
535 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
536 ret = -ETIMEDOUT;
537 }
538 bcm2835_dumpregs(host);
539 return ret;
540 }
541
bcm2835_check_data_error(struct bcm2835_host * host,u32 intmask)542 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
543 {
544 int ret = 0;
545
546 if (!host->data)
547 return 0;
548 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
549 ret = -EILSEQ;
550 if (intmask & SDHSTS_REW_TIME_OUT)
551 ret = -ETIMEDOUT;
552
553 if (ret)
554 printf("%s:%d %d\n", __func__, __LINE__, ret);
555
556 return ret;
557 }
558
bcm2835_transmit(struct bcm2835_host * host)559 static int bcm2835_transmit(struct bcm2835_host *host)
560 {
561 u32 intmask = readl(host->ioaddr + SDHSTS);
562 int ret;
563
564 /* Check for errors */
565 ret = bcm2835_check_data_error(host, intmask);
566 if (ret)
567 return ret;
568
569 ret = bcm2835_check_cmd_error(host, intmask);
570 if (ret)
571 return ret;
572
573 /* Handle wait for busy end */
574 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
575 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
576 host->use_busy = false;
577 bcm2835_finish_command(host);
578 }
579
580 /* Handle PIO data transfer */
581 if (host->data) {
582 ret = bcm2835_transfer_pio(host);
583 if (ret)
584 return ret;
585 host->blocks--;
586 if (host->blocks == 0) {
587 /* Wait for command to complete for real */
588 ret = bcm2835_wait_transfer_complete(host);
589 if (ret)
590 return ret;
591 /* Transfer complete */
592 host->data = NULL;
593 }
594 }
595
596 return 0;
597 }
598
bcm2835_set_clock(struct bcm2835_host * host,unsigned int clock)599 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
600 {
601 int div;
602 u32 clock_rate[2] = { 0 };
603
604 /* The SDCDIV register has 11 bits, and holds (div - 2). But
605 * in data mode the max is 50MHz wihout a minimum, and only
606 * the bottom 3 bits are used. Since the switch over is
607 * automatic (unless we have marked the card as slow...),
608 * chosen values have to make sense in both modes. Ident mode
609 * must be 100-400KHz, so can range check the requested
610 * clock. CMD15 must be used to return to data mode, so this
611 * can be monitored.
612 *
613 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
614 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
615 *
616 * 623->400KHz/27.8MHz
617 * reset value (507)->491159/50MHz
618 *
619 * BUT, the 3-bit clock divisor in data mode is too small if
620 * the core clock is higher than 250MHz, so instead use the
621 * SLOW_CARD configuration bit to force the use of the ident
622 * clock divisor at all times.
623 */
624
625 if (host->firmware_sets_cdiv) {
626 bcm2835_set_sdhost_clock(clock, &clock_rate[0], &clock_rate[1]);
627 clock = max(clock_rate[0], clock_rate[1]);
628 } else {
629 if (clock < 100000) {
630 /* Can't stop the clock, but make it as slow as possible
631 * to show willing
632 */
633 host->cdiv = SDCDIV_MAX_CDIV;
634 writel(host->cdiv, host->ioaddr + SDCDIV);
635 return;
636 }
637
638 div = host->max_clk / clock;
639 if (div < 2)
640 div = 2;
641 if ((host->max_clk / div) > clock)
642 div++;
643 div -= 2;
644
645 if (div > SDCDIV_MAX_CDIV)
646 div = SDCDIV_MAX_CDIV;
647
648 clock = host->max_clk / (div + 2);
649 host->cdiv = div;
650 writel(host->cdiv, host->ioaddr + SDCDIV);
651 }
652
653 host->mmc->clock = clock;
654
655 /* Calibrate some delays */
656
657 host->ns_per_fifo_word = (1000000000 / clock) *
658 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
659
660 /* Set the timeout to 500ms */
661 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
662 }
663
is_power_of_2(u64 x)664 static inline int is_power_of_2(u64 x)
665 {
666 return !(x & (x - 1));
667 }
668
bcm2835_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)669 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
670 struct mmc_data *data)
671 {
672 struct bcm2835_host *host = dev_get_priv(dev);
673 u32 edm, fsm;
674 int ret = 0;
675
676 if (data && !is_power_of_2(data->blocksize)) {
677 printf("unsupported block size (%d bytes)\n", data->blocksize);
678
679 if (cmd)
680 return -EINVAL;
681 }
682
683 edm = readl(host->ioaddr + SDEDM);
684 fsm = edm & SDEDM_FSM_MASK;
685
686 if ((fsm != SDEDM_FSM_IDENTMODE) &&
687 (fsm != SDEDM_FSM_DATAMODE) &&
688 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
689 printf("previous command (%d) not complete (EDM %08x)\n",
690 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
691 bcm2835_dumpregs(host);
692
693 if (cmd)
694 return -EILSEQ;
695
696 return 0;
697 }
698
699 if (cmd) {
700 ret = bcm2835_send_command(host, cmd, data);
701 if (!ret && !host->use_busy)
702 ret = bcm2835_finish_command(host);
703 }
704
705 /* Wait for completion of busy signal or data transfer */
706 while (host->use_busy || host->data) {
707 ret = bcm2835_transmit(host);
708 if (ret)
709 break;
710 }
711
712 return ret;
713 }
714
bcm2835_set_ios(struct udevice * dev)715 static int bcm2835_set_ios(struct udevice *dev)
716 {
717 struct bcm2835_host *host = dev_get_priv(dev);
718 struct mmc *mmc = mmc_get_mmc_dev(dev);
719
720 if (!mmc->clock || mmc->clock != host->clock) {
721 bcm2835_set_clock(host, mmc->clock);
722 host->clock = mmc->clock;
723 }
724
725 /* set bus width */
726 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
727 if (mmc->bus_width == 4)
728 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
729
730 host->hcfg |= SDHCFG_WIDE_INT_BUS;
731
732 /* Disable clever clock switching, to cope with fast core clocks */
733 host->hcfg |= SDHCFG_SLOW_CARD;
734
735 writel(host->hcfg, host->ioaddr + SDHCFG);
736
737 return 0;
738 }
739
bcm2835_add_host(struct bcm2835_host * host)740 static void bcm2835_add_host(struct bcm2835_host *host)
741 {
742 struct mmc_config *cfg = &host->plat->cfg;
743
744 cfg->f_max = host->max_clk;
745 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
746 cfg->b_max = 65535;
747
748 dev_dbg(host->dev, "f_max %d, f_min %d\n",
749 cfg->f_max, cfg->f_min);
750
751 /* host controller capabilities */
752 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
753
754 /* report supported voltage ranges */
755 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
756
757 /* Set interrupt enables */
758 host->hcfg = SDHCFG_BUSY_IRPT_EN;
759
760 bcm2835_reset_internal(host);
761 }
762
bcm2835_probe(struct udevice * dev)763 static int bcm2835_probe(struct udevice *dev)
764 {
765 struct bcm2835_plat *plat = dev_get_plat(dev);
766 struct bcm2835_host *host = dev_get_priv(dev);
767 struct mmc *mmc = mmc_get_mmc_dev(dev);
768 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
769 u32 clock_rate[2] = { ~0 };
770
771 host->dev = dev;
772 host->mmc = mmc;
773 host->plat = plat;
774 upriv->mmc = &plat->mmc;
775 plat->cfg.name = dev->name;
776
777 host->phys_addr = dev_read_addr(dev);
778 if (host->phys_addr == FDT_ADDR_T_NONE)
779 return -EINVAL;
780
781 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
782 if (!host->ioaddr)
783 return -ENOMEM;
784
785 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
786
787 bcm2835_set_sdhost_clock(0, &clock_rate[0], &clock_rate[1]);
788 host->firmware_sets_cdiv = (clock_rate[0] != ~0);
789
790 bcm2835_add_host(host);
791
792 dev_dbg(dev, "%s -> OK\n", __func__);
793
794 return 0;
795 }
796
797 static const struct udevice_id bcm2835_match[] = {
798 { .compatible = "brcm,bcm2835-sdhost" },
799 { }
800 };
801
802 static const struct dm_mmc_ops bcm2835_ops = {
803 .send_cmd = bcm2835_send_cmd,
804 .set_ios = bcm2835_set_ios,
805 };
806
bcm2835_bind(struct udevice * dev)807 static int bcm2835_bind(struct udevice *dev)
808 {
809 struct bcm2835_plat *plat = dev_get_plat(dev);
810
811 return mmc_bind(dev, &plat->mmc, &plat->cfg);
812 }
813
814 U_BOOT_DRIVER(bcm2835_sdhost) = {
815 .name = "bcm2835-sdhost",
816 .id = UCLASS_MMC,
817 .of_match = bcm2835_match,
818 .bind = bcm2835_bind,
819 .probe = bcm2835_probe,
820 .priv_auto = sizeof(struct bcm2835_host),
821 .plat_auto = sizeof(struct bcm2835_plat),
822 .ops = &bcm2835_ops,
823 };
824