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Searched refs:ADF_CSR_WR (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_ras.c13 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, 0); in enable_errsou_reporting()
16 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, 0); in enable_errsou_reporting()
22 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, in enable_errsou_reporting()
30 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, in enable_errsou_reporting()
48 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, val); in disable_errsou_reporting()
139 ADF_CSR_WR(csr, ADF_GEN4_RIMISCCTL, 0); in disable_ti_ri_error_reporting()
224 ADF_CSR_WR(csr, ADF_GEN4_SER_EN_SSMSH, in enable_ssm_error_reporting()
253 ADF_CSR_WR(csr, ADF_GEN4_INTMASKSSM, in disable_ssm_error_reporting()
304 ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR, in enable_aram_error_reporting()
307 ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR, in enable_aram_error_reporting()
[all …]
A Dadf_gen2_hw_csr_data.h40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
49 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
54 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
57 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
66 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
70 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
73 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
A Dadf_gen4_hw_csr_data.h73 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
81 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
121 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
125 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
132 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
139 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
146 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
150 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
157 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
164 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
[all …]
A Dadf_gen2_hw_data.c38 ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val); in adf_gen2_enable_error_correction()
41 ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i), val); in adf_gen2_enable_error_correction()
48 ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val); in adf_gen2_enable_error_correction()
51 ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val); in adf_gen2_enable_error_correction()
109 ADF_CSR_WR(addr, ADF_GEN2_SMIAPF0_MASK_OFFSET, val); in adf_gen2_enable_ints()
110 ADF_CSR_WR(addr, ADF_GEN2_SMIAPF1_MASK_OFFSET, ADF_GEN2_SMIA1_MASK); in adf_gen2_enable_ints()
166 ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val); in adf_gen2_set_ssm_wdtimer()
168 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke); in adf_gen2_set_ssm_wdtimer()
A Dadf_gen4_pfvf.c43 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val); in adf_gen4_enable_vf2pf_interrupts()
48 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_all_vf2pf_interrupts()
75 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
76 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, disabled | sources); in adf_gen4_disable_pending_vf2pf_interrupts()
96 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT); in adf_gen4_pfvf_send()
128 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val & ~ADF_PFVF_INT); in adf_gen4_pfvf_recv()
A Dadf_gen4_pm.c50 ADF_CSR_WR(pmisc, ADF_GEN4_PM_HOST_MSG, msg); in send_host_msg()
88 ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, pm_int_sts); in pm_bh_handler()
93 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in pm_bh_handler()
118 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in adf_gen4_handle_pm_interrupt()
155 ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, val); in adf_gen4_enable_pm()
160 ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val); in adf_gen4_enable_pm()
A Dadf_gen4_hw_data.c88 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY); in adf_gen4_enable_error_correction()
99 ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET, 0); in adf_gen4_enable_ints()
100 ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET, 0); in adf_gen4_enable_ints()
103 ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_MASK_OFFSET, 0); in adf_gen4_enable_ints()
119 ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr); in adf_gen4_init_device()
162 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low); in adf_gen4_set_ssm_wdtimer()
188 ADF_CSR_WR(csr, ADF_GEN4_MSIX_RTTABLE_OFFSET(i), i); in adf_gen4_set_msix_default_rttable()
207 ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number), in reset_ring_pair()
218 ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number), in reset_ring_pair()
457 ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number), in drain_bank()
[all …]
A Dicp_qat_hal.h126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
140 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
142 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)
A Dadf_gen2_pfvf.c60 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_enable_vf2pf_interrupts()
69 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_disable_all_vf2pf_interrupts()
101 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
106 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
224 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_msg | int_bit); in adf_gen2_pfvf_send()
255 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_send()
319 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_recv()
A Dadf_gen2_hw_data.h22 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
28 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
A Dadf_hw_arbiter.c11 ADF_CSR_WR(csr_addr, (arb_offset) + \
15 ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \
A Dadf_vf_isr.c36 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x0); in adf_enable_pf2vf_interrupts()
43 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x2); in adf_disable_pf2vf_interrupts()
A Dadf_admin.c132 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync()
581 ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val)); in adf_init_admin_comms()
582 ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val)); in adf_init_admin_comms()
A Dadf_rl.c304 ADF_CSR_WR(pmisc_addr, offset, node_id); in assign_rps_to_leaf()
319 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_leaf_to_cluster()
333 ADF_CSR_WR(pmisc_addr, offset, parent_id); in assign_cluster_to_root()
1134 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciin_tb_offset, in adf_rl_start()
1136 ADF_CSR_WR(pmisc_addr, rl_hw_data->pciout_tb_offset, in adf_rl_start()
A Dadf_accel_devices.h371 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
A Dadf_gen4_vf_mig.c476 ADF_CSR_WR(csr, misc_states[i].ofs, regv); in adf_gen4_vfmig_load_misc()
A Dqat_hal.c459 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
/linux/drivers/crypto/intel/qat/qat_dh895xcc/
A Dadf_dh895xcc_hw_data.c131 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in enable_vf2pf_interrupts()
138 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in enable_vf2pf_interrupts()
149 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in disable_all_vf2pf_interrupts()
154 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in disable_all_vf2pf_interrupts()
193 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in disable_pending_vf2pf_interrupts()
194 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5); in disable_pending_vf2pf_interrupts()
202 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in disable_pending_vf2pf_interrupts()
203 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5); in disable_pending_vf2pf_interrupts()

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