Home
last modified time | relevance | path

Searched refs:SCL_TAP_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.h77 SRI(SCL_TAP_CONTROL, SCL, id), \
147 SRI(SCL_TAP_CONTROL, SCL, id), \
222 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
223 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
314 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
315 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
576 uint32_t SCL_TAP_CONTROL; member
A Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
164 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c688 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
A Ddcn10_dpp.h64 SRI(SCL_TAP_CONTROL, DSCL, id), \
1117 uint32_t SCL_TAP_CONTROL; \
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.h106 SRI(SCL_TAP_CONTROL, DSCL, id), \
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c1175 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp401_dscl_set_scaler_manual_scale()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h285 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h483 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \

Completed in 27 milliseconds