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Searched refs:gpu_write (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/gpu/drm/msm/adreno/
A Da3xx_gpu.c221 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10); in a3xx_hw_init()
262 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR, in a3xx_hw_init()
267 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); in a3xx_hw_init()
285 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a3xx_hw_init()
326 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a3xx_hw_init()
329 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a3xx_hw_init()
338 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); in a3xx_hw_init()
347 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, in a3xx_hw_init()
361 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()
381 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); in a3xx_recover()
[all …]
A Da4xx_gpu.c108 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
111 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
149 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); in a4xx_enable_hwcg()
152 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); in a4xx_enable_hwcg()
239 gpu_write(gpu, REG_A4XX_RB_GMEM_BASE_ADDR, in a4xx_hw_init()
257 gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | in a4xx_hw_init()
321 gpu_write(gpu, REG_A4XX_CP_RB_CNTL, in a4xx_hw_init()
331 gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0); in a4xx_hw_init()
340 gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0); in a4xx_hw_init()
345 gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); in a4xx_hw_init()
[all …]
A Da5xx_power.c130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
151 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); in a530_lm_setup()
153 gpu_write(gpu, AGC_MSG_STATE, 1); in a530_lm_setup()
157 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a530_lm_setup()
158 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a530_lm_setup()
193 gpu_write(gpu, AGC_MSG_STATE, 0x80000001); in a540_lm_setup()
196 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a540_lm_setup()
197 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a540_lm_setup()
204 gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, in a540_lm_setup()
286 gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); in a5xx_lm_enable()
[all …]
A Da2xx_gpu.c161 gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_hw_init()
165 gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG, in a2xx_hw_init()
191 gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL, in a2xx_hw_init()
193 gpu_write(gpu, REG_AXXX_CP_INT_CNTL, in a2xx_hw_init()
201 gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0); in a2xx_hw_init()
202 gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK, in a2xx_hw_init()
210 gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); in a2xx_hw_init()
216 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a2xx_hw_init()
243 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a2xx_hw_init()
245 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a2xx_hw_init()
[all …]
A Da5xx_gpu.c63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
463 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
787 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
791 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
794 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
861 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
864 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
885 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
940 gpu_write(gpu, REG_A5XX_CP_RB_CNTL, in a5xx_hw_init()
955 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
[all …]
A Da6xx_gpu.c89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
490 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
583 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, in a6xx_set_ubwc_config()
595 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a6xx_set_ubwc_config()
605 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, in a6xx_set_ubwc_config()
878 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
884 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1088 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1095 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1111 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, in hw_init()
[all …]
A Da6xx_gpu_state.c163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
227 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
230 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
264 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
268 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
297 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk); in a6xx_get_vbif_debugbus_block()
439 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, in a6xx_get_debugbus()
442 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, in a6xx_get_debugbus()
1456 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
[all …]
A Da5xx_debugfs.c21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
58 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
A Da2xx_gpummu.c53 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
68 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
167 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
/linux/drivers/gpu/drm/panfrost/
A Dpanfrost_perfcnt.c57 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_dump_locked()
119 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_enable_locked()
153 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_enable_locked()
157 gpu_write(pfdev, GPU_PERFCNT_CFG, cfg); in panfrost_perfcnt_enable_locked()
190 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0x0); in panfrost_perfcnt_disable_locked()
193 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_disable_locked()
194 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_disable_locked()
326 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_init()
328 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0); in panfrost_perfcnt_init()
343 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_fini()
[all …]
A Dpanfrost_gpu.c46 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_irq_handler()
55 gpu_write(pfdev, GPU_INT_CLEAR, state); in panfrost_gpu_irq_handler()
65 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_soft_reset()
70 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); in panfrost_gpu_soft_reset()
77 gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); in panfrost_gpu_soft_reset()
89 gpu_write(pfdev, GPU_INT_MASK, in panfrost_gpu_soft_reset()
143 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); in panfrost_gpu_init_quirks()
152 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); in panfrost_gpu_init_quirks()
168 gpu_write(pfdev, GPU_JM_CONFIG, quirks); in panfrost_gpu_init_quirks()
422 gpu_write(pfdev, SHADER_PWRON_LO, in panfrost_gpu_power_on()
[all …]
A Dpanfrost_regs.h335 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) macro
/linux/drivers/gpu/drm/etnaviv/
A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
A Detnaviv_gpu.c477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
536 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
539 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
672 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
677 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
762 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
779 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
785 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
1341 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
[all …]
A Detnaviv_perfmon.c44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
A Detnaviv_gpu.h167 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/panthor/
A Dpanthor_device.h297 gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
313 gpu_write(ptdev, __reg_prefix ## _INT_CLEAR, status); \
320 gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
328 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
337 gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \
338 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \
A Dpanthor_gpu.c260 gpu_write(ptdev, pwroff_reg, mask); in panthor_gpu_block_power_off()
263 gpu_write(ptdev, pwroff_reg + 4, mask >> 32); in panthor_gpu_block_power_off()
321 gpu_write(ptdev, pwron_reg, mask); in panthor_gpu_block_power_on()
324 gpu_write(ptdev, pwron_reg + 4, mask >> 32); in panthor_gpu_block_power_on()
390 gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
429 gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
430 gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
A Dpanthor_mmu.c531 gpu_write(ptdev, AS_COMMAND(as_nr), cmd); in write_cmd()
566 gpu_write(ptdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); in lock_region()
567 gpu_write(ptdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); in lock_region()
620 gpu_write(ptdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); in panthor_mmu_as_enable()
637 gpu_write(ptdev, AS_TRANSTAB_LO(as_nr), 0); in panthor_mmu_as_disable()
638 gpu_write(ptdev, AS_TRANSTAB_HI(as_nr), 0); in panthor_mmu_as_disable()
640 gpu_write(ptdev, AS_MEMATTR_LO(as_nr), 0); in panthor_mmu_as_disable()
641 gpu_write(ptdev, AS_MEMATTR_HI(as_nr), 0); in panthor_mmu_as_disable()
644 gpu_write(ptdev, AS_TRANSCFG_HI(as_nr), 0); in panthor_mmu_as_disable()
783 gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask); in panthor_vm_active()
[all …]
A Dpanthor_fw.c959 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_init_global_iface()
987 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1018 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1044 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_pre_reset()
1275 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ring_csg_doorbells()
1290 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ping_work()
A Dpanthor_regs.h233 #define gpu_write(dev, reg, data) \ macro
/linux/drivers/gpu/drm/msm/
A Dmsm_gpu.h565 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/i915/gem/selftests/
A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, in gpu_write() function
1175 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1900 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()

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