| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| A D | smu_cmn.h | 131 enum pp_mp1_state mp1_state);
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| A D | smu_cmn.c | 1114 enum pp_mp1_state mp1_state) in smu_cmn_set_mp1_state() argument
1119 switch (mp1_state) { in smu_cmn_set_mp1_state()
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| A D | amdgpu_smu.c | 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
2499 enum pp_mp1_state mp1_state) in smu_set_mp1_state() argument
2509 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); in smu_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_drv.c | 2470 adev->mp1_state = PP_MP1_STATE_UNLOAD; in amdgpu_pci_shutdown()
2472 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pci_shutdown()
2770 adev->mp1_state = PP_MP1_STATE_UNLOAD; in amdgpu_pmops_runtime_suspend()
2779 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pmops_runtime_suspend()
2784 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pmops_runtime_suspend()
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| A D | amdgpu_device.c | 3503 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); in amdgpu_device_ip_suspend_phase2()
3506 adev->mp1_state, r); in amdgpu_device_ip_suspend_phase2()
5508 adev->mp1_state = PP_MP1_STATE_SHUTDOWN; in amdgpu_device_set_mp1_state()
5511 adev->mp1_state = PP_MP1_STATE_RESET; in amdgpu_device_set_mp1_state()
5514 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_device_set_mp1_state()
5522 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_device_unset_mp1_state()
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| A D | amdgpu.h | 1098 enum pp_mp1_state mp1_state; member
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| /linux/drivers/gpu/drm/amd/pm/ |
| A D | amdgpu_dpm.c | 166 enum pp_mp1_state mp1_state) in amdgpu_dpm_set_mp1_state() argument
171 if (mp1_state == PP_MP1_STATE_FLR) { in amdgpu_dpm_set_mp1_state()
180 mp1_state); in amdgpu_dpm_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/pm/inc/ |
| A D | amdgpu_dpm.h | 420 enum pp_mp1_state mp1_state);
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.c | 1985 enum pp_mp1_state mp1_state) in aldebaran_set_mp1_state() argument
1987 switch (mp1_state) { in aldebaran_set_mp1_state()
1989 return smu_cmn_set_mp1_state(smu, mp1_state); in aldebaran_set_mp1_state()
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| A D | smu_v13_0_7_ppt.c | 2514 enum pp_mp1_state mp1_state) in smu_v13_0_7_set_mp1_state() argument
2518 switch (mp1_state) { in smu_v13_0_7_set_mp1_state()
2520 ret = smu_cmn_set_mp1_state(smu, mp1_state); in smu_v13_0_7_set_mp1_state()
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| A D | smu_v13_0_0_ppt.c | 2755 enum pp_mp1_state mp1_state) in smu_v13_0_0_set_mp1_state() argument
2759 switch (mp1_state) { in smu_v13_0_0_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| A D | amd_powerplay.c | 912 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) in pp_dpm_set_mp1_state() argument
923 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); in pp_dpm_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_2_ppt.c | 2006 enum pp_mp1_state mp1_state) in smu_v14_0_2_set_mp1_state() argument
2010 switch (mp1_state) { in smu_v14_0_2_set_mp1_state()
2012 ret = smu_cmn_set_mp1_state(smu, mp1_state); in smu_v14_0_2_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | hwmgr.h | 359 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| A D | amdgpu_smu.h | 967 enum pp_mp1_state mp1_state);
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | kgd_pp_interface.h | 409 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega12_hwmgr.c | 2842 enum pp_mp1_state mp1_state) in vega12_set_mp1_state() argument
2847 switch (mp1_state) { in vega12_set_mp1_state()
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| A D | vega20_hwmgr.c | 3181 enum pp_mp1_state mp1_state) in vega20_set_mp1_state() argument
3186 switch (mp1_state) { in vega20_set_mp1_state()
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| A D | vega10_hwmgr.c | 5658 enum pp_mp1_state mp1_state) in vega10_set_mp1_state() argument
5663 switch (mp1_state) { in vega10_set_mp1_state()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | sienna_cichlid_ppt.c | 4211 enum pp_mp1_state mp1_state) in sienna_cichlid_set_mp1_state() argument
4215 switch (mp1_state) { in sienna_cichlid_set_mp1_state()
4217 ret = smu_cmn_set_mp1_state(smu, mp1_state); in sienna_cichlid_set_mp1_state()
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