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Searched refs:phy_modify (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/net/phy/
A Dvitesse.c227 phy_modify(phydev, 0x0c, 0x0300, 0x0200); in vsc73xx_config_init()
249 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
252 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc738x_config_init()
253 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc738x_config_init()
256 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
314 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc739x_config_init()
317 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc739x_config_init()
318 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc739x_config_init()
321 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc739x_config_init()
327 phy_modify(phydev, 0x16, 0x0fc0, 0x0240); in vsc739x_config_init()
[all …]
A Ddp83867.c469 return phy_modify(phydev, DP83867_CFG2, in dp83867_set_downshift()
767 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, in dp83867_config_init()
963 err = phy_modify(phydev, MII_DP83867_PHYCTRL, in dp83867_phy_reset()
1014 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, in dp83867_loopback()
1033 return phy_modify(phydev, DP83867_LEDCR2, in dp83867_led_brightness_set()
1093 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index), in dp83867_led_hw_control_set()
1098 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0); in dp83867_led_hw_control_set()
1172 return phy_modify(phydev, DP83867_LEDCR2, in dp83867_led_polarity_set()
A Dnxp-tja11xx.c121 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
170 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, in tja11xx_wakeup()
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
343 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, in tja11xx_config_init()
A Ddp83869.c468 return phy_modify(phydev, DP83869_CFG2, in dp83869_set_downshift()
668 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83869_configure_fiber()
797 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, in dp83869_config_init()
A Dmarvell.c846 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL, in m88e3016_config_init()
862 return phy_modify(phydev, MII_M1111_PHY_EXT_SR, in m88e1111_config_init_hwcfg_mode()
888 return phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_config_init_rgmii_delays()
971 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR, in m88e1111_config_init_1000basex()
1061 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_set_downshift()
1125 err = phy_modify(phydev, MII_M1011_PHY_SCR, in m88e1011_set_downshift()
1291 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1408 err = phy_modify(phydev, 0x1e, 0x0fc0, in m88e1145_config_init_rgmii()
1537 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
2113 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, in m88e1510_loopback()
[all …]
A Ddp83822.c452 err = phy_modify(phydev, MII_DP83822_CTRL_2, in dp83822_config_init()
480 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83822_config_init()
A Dbcm54140.c487 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); in bcm54140_b0_workaround()
491 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); in bcm54140_b0_workaround()
A Dphy_device.c2282 return phy_modify(phydev, MII_BMCR, in genphy_setup_forced()
2373 return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, in genphy_restart_aneg()
2480 err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100, in genphy_c37_config_aneg()
2790 ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res); in genphy_soft_reset()
2917 phy_modify(phydev, MII_BMCR, ~0, ctl); in genphy_loopback()
2925 phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0); in genphy_loopback()
A Dintel-xway.c227 return phy_modify(phydev, XWAY_MDIO_MIICTRL, in xway_gphy_rgmii_init()
A Dmicrochip.c465 return phy_modify(phydev, LAN937X_MODE_CTRL_STATUS_REG, in lan937x_tx_set_mdix()
A Dmxl-gpy.c398 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | in gpy_config_mdix()
809 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); in gpy_loopback()
A Dphy-core.c852 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) in phy_modify() function
862 EXPORT_SYMBOL_GPL(phy_modify);
A Dadin.c379 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, in adin_set_downshift()
432 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2, in adin_set_edpd()
A Dmicrel.c803 return phy_modify(phydev, MII_KSZPHY_CTRL_2, in ksz8081_config_mdix()
1490 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX, in ksz9131_config_mdix()
1626 ret = phy_modify(phydev, MII_BMCR, in ksz9x31_cable_test_start()
1800 rv = phy_modify(phydev, MII_CTRL1000, in ksz9x31_cable_test_get_status()
1838 return phy_modify(phydev, MII_BMCR, in ksz886x_config_mdix()
2245 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100, in lan8814_cable_test_start()
4124 phy_modify(phydev, LAN8841_OUTPUT_CTRL, in lan8841_config_intr()
A Dmicrochip_t1.c746 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in microchip_cable_test_start_common()
1387 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET); in lan887x_phy_reset()
A Dbcm-phy-lib.c810 return phy_modify(phydev, MII_BCM54XX_LRECR, LRECR_SPEED100, ctl); in bcm_setup_lre_forced()
A Dmotorcomm.c643 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, in yt8531_set_wol()
654 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, in yt8531_set_wol()
A Dbroadcom.c1053 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP | in bcm5221_config_aneg()
/linux/drivers/net/ethernet/realtek/
A Dr8169_phy_config.c482 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); in rtl8168d_1_hw_phy_config()
483 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); in rtl8168d_1_hw_phy_config()
499 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_1_hw_phy_config()
520 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_2_hw_phy_config()
1082 phy_modify(phydev, 0x17, 0xff00, 0x0800); in rtl8125b_hw_phy_config()
/linux/drivers/net/phy/qcom/
A Dqcom-phy-lib.c87 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); in at803x_set_wol()
92 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); in at803x_set_wol()
A Dat803x.c226 phy_modify(phydev, MII_BMCR, 0, value); in at803x_suspend()
233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); in at803x_resume()
480 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); in at803x_config_init()
A Dqca83xx.c210 phy_modify(phydev, MII_BMCR, mask, 0); in qca8327_suspend()
A Dqca807x.c661 ret = phy_modify(phydev, in qca807x_sfp_insert()
/linux/include/linux/
A Dphy.h1428 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
1474 return phy_modify(phydev, regnum, 0, val); in phy_set_bits()
1485 return phy_modify(phydev, regnum, val, 0); in phy_clear_bits()
/linux/drivers/net/phy/mscc/
A Dmscc_main.c2103 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()

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