Searched refs:phy_offset (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dkl_phy_regs.h | 34 #define _DKL_REG_BANK_OFFSET(phy_offset) \ argument
35 ((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1))
36 #define _DKL_REG_BANK_IDX(phy_offset) \ argument
37 (((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
39 #define _DKL_REG(tc_port, phy_offset) \ argument
42 _DKL_REG_BANK_OFFSET(phy_offset), \
43 .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
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| /linux/drivers/net/wireless/broadcom/b43/ |
| A D | phy_lp.c | 612 u16 phy_offset; member
620 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
622 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
623 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
624 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
625 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
626 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
628 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
629 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
630 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
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| /linux/drivers/iio/adc/ |
| A D | exynos_adc.c | 160 int phy_offset; member
234 regmap_write(info->pmu_map, info->data->phy_offset, 1); in exynos_adc_v1_init_hw()
252 regmap_write(info->pmu_map, info->data->phy_offset, 0); in exynos_adc_v1_exit_hw()
280 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
292 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
392 regmap_write(info->pmu_map, info->data->phy_offset, 1); in exynos_adc_v2_init_hw()
410 regmap_write(info->pmu_map, info->data->phy_offset, 0); in exynos_adc_v2_exit_hw()
440 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
453 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
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| /linux/drivers/net/wireless/realtek/rtw89/ |
| A D | pci.c | 23 u32 *phy_offset) in rtw89_pci_get_phy_offset_by_link_speed() argument
36 *phy_offset = R_RAC_DIRECT_OFFSET_G1; in rtw89_pci_get_phy_offset_by_link_speed()
38 *phy_offset = R_RAC_DIRECT_OFFSET_G2; in rtw89_pci_get_phy_offset_by_link_speed()
2365 u32 phy_offset; in rtw89_pci_disable_eq() local
2409 u32 phy_offset; in rtw89_pci_ber() local
2414 phy_offset = R_RAC_DIRECT_OFFSET_G1; in rtw89_pci_ber()
2418 phy_offset = R_RAC_DIRECT_OFFSET_G2; in rtw89_pci_ber()
3781 u32 val, phy_offset; in rtw89_pci_filter_out() local
3797 phy_offset = R_RAC_DIRECT_OFFSET_G1; in rtw89_pci_filter_out()
3799 phy_offset = R_RAC_DIRECT_OFFSET_G2; in rtw89_pci_filter_out()
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| /linux/drivers/net/ethernet/intel/ixgbe/ |
| A D | ixgbe_phy.c | 1404 u16 phy_offset, control, eword, edata, block_crc; in ixgbe_reset_phy_nl() local
1461 &phy_offset); in ixgbe_reset_phy_nl()
1469 hw->phy.ops.write_reg(hw, phy_offset, in ixgbe_reset_phy_nl()
1472 phy_offset); in ixgbe_reset_phy_nl()
1474 phy_offset++; in ixgbe_reset_phy_nl()
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