1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef ARCH_HELPERS_H
9 #define ARCH_HELPERS_H
10
11 #include <arch.h>
12
13 #include <fwk_noreturn.h>
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <string.h>
18
19 /**********************************************************************
20 * Macros which create inline functions to read or write CPU system
21 * registers
22 *********************************************************************/
23
24 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
25 static inline unsigned long read_##_name(void) \
26 { \
27 unsigned long v; \
28 __asm__ volatile("mrs %0, " #_reg_name : "=r"(v)); \
29 return v; \
30 }
31
32 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
33 static inline void write_##_name(unsigned long v) \
34 { \
35 __asm__ volatile("msr " #_reg_name ", %0" : : "r"(v)); \
36 }
37
38 #define SYSREG_WRITE_CONST(reg_name, v) \
39 __asm__ volatile("msr " #reg_name ", %0" : : "i"(v))
40
41 /* Define read function for system register */
42 #define DEFINE_SYSREG_READ_FUNC(_name) _DEFINE_SYSREG_READ_FUNC(_name, _name)
43
44 /* Define read & write function for system register */
45 #define DEFINE_SYSREG_RW_FUNCS(_name) \
46 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
47 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
48
49 /* Define read & write function for renamed system register */
50 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
51 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
52 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
53
54 /* Define read function for renamed system register */
55 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
56 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
57
58 /* Define write function for renamed system register */
59 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
60 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
61
62 /**********************************************************************
63 * Macros to create inline functions for system instructions
64 *********************************************************************/
65
66 /* Define function for simple system instruction */
67 #define DEFINE_SYSOP_FUNC(_op) \
68 static inline void _op(void) \
69 { \
70 __asm__(#_op); \
71 }
72
73 /* Define function for system instruction with type specifier */
74 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
75 static inline void _op##_type(void) \
76 { \
77 __asm__(#_op " " #_type); \
78 }
79
80 /* Define function for system instruction with register parameter */
81 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
82 static inline void _op##_type(uint64_t v) \
83 { \
84 __asm__(#_op " " #_type ", %0" : : "r"(v)); \
85 }
86
87 /*******************************************************************************
88 * TLB maintenance accessor prototypes
89 ******************************************************************************/
90
91 #if ERRATA_A57_813419
92 /*
93 * Define function for TLBI instruction with type specifier that implements
94 * the workaround for errata 813419 of Cortex-A57.
95 */
96 # define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type) \
97 static inline void tlbi##_type(void) \
98 { \
99 __asm__("tlbi " #_type \
100 "\n" \
101 "dsb ish\n" \
102 "tlbi " #_type); \
103 }
104
105 /*
106 * Define function for TLBI instruction with register parameter that implements
107 * the workaround for errata 813419 of Cortex-A57.
108 */
109 # define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
110 static inline void tlbi##_type(uint64_t v) \
111 { \
112 __asm__("tlbi " #_type \
113 ", %0\n" \
114 "dsb ish\n" \
115 "tlbi " #_type ", %0" \
116 : \
117 : "r"(v)); \
118 }
119 #endif /* ERRATA_A57_813419 */
120
121 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
122 /*
123 * Define function for DC instruction with register parameter that enables
124 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
125 */
126 # define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
127 static inline void dc##_name(uint64_t v) \
128 { \
129 __asm__("dc " #_type ", %0" : : "r"(v)); \
130 }
131 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
132
133 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
134 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
135 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
136 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
137 #if ERRATA_A57_813419
138 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
139 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
140 #else
141 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
142 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
143 #endif
144 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
145
146 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
147 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
148 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
149 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
150 #if ERRATA_A57_813419
151 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
152 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
153 #else
154 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
155 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
156 #endif
157
158 /*******************************************************************************
159 * Cache maintenance accessor prototypes
160 ******************************************************************************/
161 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
162 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
163 #if ERRATA_A53_827319
164 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
165 #else
166 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
167 #endif
168 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
169 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
170 #else
171 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
172 #endif
173 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
174 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
175 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
176 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
177 #else
178 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
179 #endif
180 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
181
182 /*******************************************************************************
183 * Address translation accessor prototypes
184 ******************************************************************************/
185 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
186 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
187 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
188 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
189 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
190 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
191 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
192
193 void flush_dcache_range(uintptr_t addr, size_t size);
194 void clean_dcache_range(uintptr_t addr, size_t size);
195 void inv_dcache_range(uintptr_t addr, size_t size);
196
197 void dcsw_op_louis(unsigned long op_type);
198 void dcsw_op_all(unsigned long op_type);
199
200 void disable_mmu_el1(void);
201 void disable_mmu_el3(void);
202 void disable_mmu_icache_el1(void);
203 void disable_mmu_icache_el3(void);
204
205 /*******************************************************************************
206 * Misc. accessor prototypes
207 ******************************************************************************/
208
209 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
210 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
211
212 DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)213 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
214 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
215 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
216 DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
217 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
218 DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
219 DEFINE_SYSREG_READ_FUNC(CurrentEl)
220 DEFINE_SYSREG_READ_FUNC(ctr_el0)
221 DEFINE_SYSREG_RW_FUNCS(daif)
222 DEFINE_SYSREG_RW_FUNCS(spsr_el1)
223 DEFINE_SYSREG_RW_FUNCS(spsr_el2)
224 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
225 DEFINE_SYSREG_RW_FUNCS(elr_el1)
226 DEFINE_SYSREG_RW_FUNCS(elr_el2)
227 DEFINE_SYSREG_RW_FUNCS(elr_el3)
228
229 DEFINE_SYSOP_FUNC(wfi)
230 DEFINE_SYSOP_FUNC(wfe)
231 DEFINE_SYSOP_FUNC(sev)
232 DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
233 DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
234 DEFINE_SYSOP_TYPE_FUNC(dmb, st)
235 DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
236 DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
237 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
238 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
239 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
240 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
241 DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
242 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
243 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
244 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
245 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
246 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
247 DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
248 DEFINE_SYSOP_FUNC(isb)
249
250 static inline void enable_irq(void)
251 {
252 /*
253 * The compiler memory barrier will prevent the compiler from
254 * scheduling non-volatile memory access after the write to the
255 * register.
256 *
257 * This could happen if some initialization code issues non-volatile
258 * accesses to an area used by an interrupt handler, in the assumption
259 * that it is safe as the interrupts are disabled at the time it does
260 * that (according to program order). However, non-volatile accesses
261 * are not necessarily in program order relatively with volatile inline
262 * assembly statements (and volatile accesses).
263 */
264 COMPILER_BARRIER();
265 write_daifclr(DAIF_IRQ_BIT);
266 isb();
267 }
268
enable_fiq(void)269 static inline void enable_fiq(void)
270 {
271 COMPILER_BARRIER();
272 write_daifclr(DAIF_FIQ_BIT);
273 isb();
274 }
275
enable_serror(void)276 static inline void enable_serror(void)
277 {
278 COMPILER_BARRIER();
279 write_daifclr(DAIF_ABT_BIT);
280 isb();
281 }
282
enable_debug_exceptions(void)283 static inline void enable_debug_exceptions(void)
284 {
285 COMPILER_BARRIER();
286 write_daifclr(DAIF_DBG_BIT);
287 isb();
288 }
289
disable_irq(void)290 static inline void disable_irq(void)
291 {
292 COMPILER_BARRIER();
293 write_daifset(DAIF_IRQ_BIT);
294 isb();
295 }
296
disable_fiq(void)297 static inline void disable_fiq(void)
298 {
299 COMPILER_BARRIER();
300 write_daifset(DAIF_FIQ_BIT);
301 isb();
302 }
303
disable_serror(void)304 static inline void disable_serror(void)
305 {
306 COMPILER_BARRIER();
307 write_daifset(DAIF_ABT_BIT);
308 isb();
309 }
310
disable_debug_exceptions(void)311 static inline void disable_debug_exceptions(void)
312 {
313 COMPILER_BARRIER();
314 write_daifset(DAIF_DBG_BIT);
315 isb();
316 }
317
318 #if !ERROR_DEPRECATED
319 uint32_t get_afflvl_shift(uint32_t);
320 uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
321
322 noreturn void eret(
323 uint64_t x0,
324 uint64_t x1,
325 uint64_t x2,
326 uint64_t x3,
327 uint64_t x4,
328 uint64_t x5,
329 uint64_t x6,
330 uint64_t x7);
331 #endif
332 noreturn void smc(
333 uint64_t x0,
334 uint64_t x1,
335 uint64_t x2,
336 uint64_t x3,
337 uint64_t x4,
338 uint64_t x5,
339 uint64_t x6,
340 uint64_t x7);
341
342 /*******************************************************************************
343 * System register accessor prototypes
344 ******************************************************************************/
345 DEFINE_SYSREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)346 DEFINE_SYSREG_READ_FUNC(mpidr_el1)
347 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
348
349 DEFINE_SYSREG_RW_FUNCS(scr_el3)
350 DEFINE_SYSREG_RW_FUNCS(hcr_el2)
351
352 DEFINE_SYSREG_RW_FUNCS(vbar_el1)
353 DEFINE_SYSREG_RW_FUNCS(vbar_el2)
354 DEFINE_SYSREG_RW_FUNCS(vbar_el3)
355
356 DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
357 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
358 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
359
360 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
361 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
362 DEFINE_SYSREG_RW_FUNCS(actlr_el3)
363
364 DEFINE_SYSREG_RW_FUNCS(esr_el1)
365 DEFINE_SYSREG_RW_FUNCS(esr_el2)
366 DEFINE_SYSREG_RW_FUNCS(esr_el3)
367
368 DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
369 DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
370 DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
371
372 DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
373 DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
374 DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
375
376 DEFINE_SYSREG_RW_FUNCS(far_el1)
377 DEFINE_SYSREG_RW_FUNCS(far_el2)
378 DEFINE_SYSREG_RW_FUNCS(far_el3)
379
380 DEFINE_SYSREG_RW_FUNCS(mair_el1)
381 DEFINE_SYSREG_RW_FUNCS(mair_el2)
382 DEFINE_SYSREG_RW_FUNCS(mair_el3)
383
384 DEFINE_SYSREG_RW_FUNCS(amair_el1)
385 DEFINE_SYSREG_RW_FUNCS(amair_el2)
386 DEFINE_SYSREG_RW_FUNCS(amair_el3)
387
388 DEFINE_SYSREG_READ_FUNC(rvbar_el1)
389 DEFINE_SYSREG_READ_FUNC(rvbar_el2)
390 DEFINE_SYSREG_READ_FUNC(rvbar_el3)
391
392 DEFINE_SYSREG_RW_FUNCS(rmr_el1)
393 DEFINE_SYSREG_RW_FUNCS(rmr_el2)
394 DEFINE_SYSREG_RW_FUNCS(rmr_el3)
395
396 DEFINE_SYSREG_RW_FUNCS(tcr_el1)
397 DEFINE_SYSREG_RW_FUNCS(tcr_el2)
398 DEFINE_SYSREG_RW_FUNCS(tcr_el3)
399
400 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
401 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
402 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
403
404 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
405
406 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
407
408 DEFINE_SYSREG_RW_FUNCS(cptr_el2)
409 DEFINE_SYSREG_RW_FUNCS(cptr_el3)
410
411 DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
412 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
413 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
414 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
415 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
416 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
417 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
418 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
419 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
420 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
421 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
422 DEFINE_SYSREG_READ_FUNC(cntpct_el0)
423 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
424
425 #define get_cntp_ctl_enable(x) \
426 (((x) >> CNTP_CTL_ENABLE_SHIFT) & CNTP_CTL_ENABLE_MASK)
427 #define get_cntp_ctl_imask(x) \
428 (((x) >> CNTP_CTL_IMASK_SHIFT) & CNTP_CTL_IMASK_MASK)
429 #define get_cntp_ctl_istatus(x) \
430 (((x) >> CNTP_CTL_ISTATUS_SHIFT) & CNTP_CTL_ISTATUS_MASK)
431
432 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
433 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
434
435 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
436 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
437
438 DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
439
440 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
441
442 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
443 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
444
445 DEFINE_SYSREG_READ_FUNC(isr_el1)
446
447 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
448 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
449 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
450 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
451
452 /* GICv3 System Registers */
453
454 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
455 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
456 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
457 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
458 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
459 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
460 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
461 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
462 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
463 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
464 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
465 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
466 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
467 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
468 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
469 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
470
471 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
472 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
473 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
474 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
475 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
476
477 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
478 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
479 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
480 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
481
482 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
483
484 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
485 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
486
487 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
488 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
489
490 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
491 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
492 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
493 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
494 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
495 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
496
497 /* Armv8.2 Registers */
498 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
499
500 /* Armv8.3 Pointer Authentication Registers */
501 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
502 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
503
504 #define IS_IN_EL(x) (GET_EL(read_CurrentEl()) == MODE_EL##x)
505
506 #define IS_IN_EL1() IS_IN_EL(1)
507 #define IS_IN_EL2() IS_IN_EL(2)
508 #define IS_IN_EL3() IS_IN_EL(3)
509
510 static inline unsigned int get_current_el(void)
511 {
512 return (unsigned int)GET_EL(read_CurrentEl());
513 }
514
515 /*
516 * Check if an EL is implemented from AA64PFR0 register fields.
517 */
el_implemented(unsigned int el)518 static inline uint64_t el_implemented(unsigned int el)
519 {
520 if (el > 3U) {
521 return EL_IMPL_NONE;
522 } else {
523 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
524
525 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
526 }
527 }
528
529 #if !ERROR_DEPRECATED
530 # define EL_IMPLEMENTED(_el) el_implemented(_el)
531 #endif
532
533 /* Previously defined accesor functions with incomplete register names */
534
535 #define read_current_el() read_CurrentEl()
536
537 #define dsb() dsbsy()
538
539 #define read_midr() read_midr_el1()
540
541 #define read_mpidr() read_mpidr_el1()
542
543 #define read_scr() read_scr_el3()
544 #define write_scr(_v) write_scr_el3(_v)
545
546 #define read_hcr() read_hcr_el2()
547 #define write_hcr(_v) write_hcr_el2(_v)
548
549 #define read_cpacr() read_cpacr_el1()
550 #define write_cpacr(_v) write_cpacr_el1(_v)
551
552 /*
553 * This variable is used to ensure spurious nested calls won't
554 * enable interrupts. This is been defined in arch_main.c
555 */
556 extern unsigned int critical_section_nest_level;
557
558 /*!
559 * \brief Enables global CPU interrupts.
560 *
561 * \note inline is necessary as this call can be used in performance sensitive
562 * path
563 */
arch_interrupts_enable(unsigned int not_used)564 inline static void arch_interrupts_enable(unsigned int not_used)
565 {
566 /* Decrement critical_section_nest_level only if in critical section */
567 if (critical_section_nest_level > 0) {
568 critical_section_nest_level--;
569 }
570
571 /* Enable interrupts globally if now outside critical section */
572 if (critical_section_nest_level == 0) {
573 enable_irq();
574 }
575 }
576
577 /*!
578 * \brief Disables global CPU interrupts.
579
580 * \note inline is necessary as this call can be used in performance sensitive
581 * path
582 */
arch_interrupts_disable()583 inline static unsigned int arch_interrupts_disable()
584 {
585 disable_irq();
586 critical_section_nest_level++;
587
588 return 0;
589 }
590
591 /*!
592 * \brief Suspend execution of current CPU.
593
594 * \note CPU will be woken up by receiving interrupts.
595 *
596 */
arch_suspend(void)597 inline static void arch_suspend(void)
598 {
599 wfe();
600 }
601
602 #endif /* ARCH_HELPERS_H */
603