1/*
2 * Copyright 2022 The Hafnium Authors.
3 *
4 * Use of this source code is governed by a BSD-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/BSD-3-Clause.
7 */
8
9/dts-v1/;
10
11/ {
12	compatible = "arm,ffa-core-manifest-1.0";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	attribute {
17		spmc_id = <0x8000>;
18		maj_ver = <0x1>;
19		min_ver = <0x1>;
20		exec_state = <0x0>;
21		load_address = <0x0 0x6000000>;
22		entrypoint = <0x0 0x6000000>;
23		binary_size = <0x80000>;
24	};
25
26	hypervisor {
27		compatible = "hafnium,hafnium";
28		vm1 {
29			is_ffa_partition;
30			load_address = <0x6280000>;
31			debug_name = "op-tee";
32			vcpu_count = <8>;
33			mem_size = <0xd00000>;
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,armv8";
44			reg = <0x0 0x000>;
45			enable-method = "psci";
46		};
47		/*
48		 * SPMC (Hafnium) requires secondary core nodes are declared
49		 * in descending order.
50		 */
51		cpu7: cpu@10300 {
52			device_type = "cpu";
53			compatible = "arm,armv8";
54			reg = <0x0 0x10300>;
55			enable-method = "psci";
56		};
57		cpu6: cpu@10200 {
58			device_type = "cpu";
59			compatible = "arm,armv8";
60			reg = <0x0 0x10200>;
61			enable-method = "psci";
62		};
63		cpu5: cpu@10100 {
64			device_type = "cpu";
65			compatible = "arm,armv8";
66			reg = <0x0 0x10100>;
67			enable-method = "psci";
68		};
69		cpu4: cpu@10000 {
70			device_type = "cpu";
71			compatible = "arm,armv8";
72			reg = <0x0 0x10000>;
73			enable-method = "psci";
74		};
75		cpu3: cpu@300 {
76			device_type = "cpu";
77			compatible = "arm,armv8";
78			reg = <0x0 0x300>;
79			enable-method = "psci";
80		};
81		cpu2: cpu@200 {
82			device_type = "cpu";
83			compatible = "arm,armv8";
84			reg = <0x0 0x200>;
85			enable-method = "psci";
86		};
87		cpu1: cpu@100 {
88			device_type = "cpu";
89			compatible = "arm,armv8";
90			reg = <0x0 0x100>;
91			enable-method = "psci";
92		};
93	};
94
95	/* Secure world memory */
96	memory@0 {
97		device_type = "memory";
98		reg = <0x0 0x6000000 0x0 0x2000000>, /* Trusted DRAM */
99		      <0x0 0xfc000000 0x0 0x4000000>; /* NS DRAM */
100	};
101
102	/* NS memory */
103	memory@1 {
104		device_type = "ns-memory";
105		reg = <0x0 0x80000000 0x0 0x7c000000>,
106		      <0x8 0x80000000 0x1 0x80000000>,
107		      <0x00008800 0x80000000 0x0 0x7f000000>;
108
109	};
110
111	/* Device memory */
112	memory@2 {
113		device_type = "device-memory";
114		reg = <0x0 0x1c090000 0x0 0x40000>; /* UART */
115	};
116};
117