1# i386/x86_64 cpu features 2config BR2_X86_CPU_HAS_MMX 3 bool 4config BR2_X86_CPU_HAS_3DNOW 5 bool 6config BR2_X86_CPU_HAS_SSE 7 bool 8config BR2_X86_CPU_HAS_SSE2 9 bool 10config BR2_X86_CPU_HAS_SSE3 11 bool 12config BR2_X86_CPU_HAS_SSSE3 13 bool 14config BR2_X86_CPU_HAS_SSE4 15 bool 16config BR2_X86_CPU_HAS_SSE42 17 bool 18config BR2_X86_CPU_HAS_AVX 19 bool 20config BR2_X86_CPU_HAS_AVX2 21 bool 22 23# BR2_X86_CPU_HAS_AVX512 implies the following AVX512 extensions: 24# AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL 25# This subset is common to Intel Xeon (excl Xeon Phi), AMD Zen 4, and 26# the x86-64-v4 psABI. 27# 28# Only select BR2_X86_CPU_HAS_AVX512 if the CPU supports this entire 29# subset of extensions. 30config BR2_X86_CPU_HAS_AVX512 31 bool 32 33# This list of CPU architecture variant is (loosely) ordered according 34# to the gcc documentation at 35# https://gcc.gnu.org/onlinedocs/gcc-13.2.0/gcc/x86-Options.html 36choice 37 prompt "Target Architecture Variant" 38 default BR2_x86_i586 if BR2_i386 39 depends on BR2_i386 || BR2_x86_64 40 help 41 Specific CPU variant to use 42 43config BR2_x86_i486 44 bool "i486" 45 depends on !BR2_x86_64 46config BR2_x86_i586 47 bool "i586" 48 depends on !BR2_x86_64 49config BR2_x86_x1000 50 bool "x1000" 51 depends on !BR2_x86_64 52 help 53 The Intel X1000 is a Pentium class microprocessor in the 54 Quark (sub-Atom) Product Line. The X1000 has a bug on the 55 lock prefix requiring that prefix must be stripped at build 56 time. 57 58 See https://en.wikipedia.org/wiki/Intel_Quark 59 60config BR2_x86_i686 61 bool "i686" 62 depends on !BR2_x86_64 63config BR2_x86_pentiumpro 64 bool "pentium pro" 65 depends on !BR2_x86_64 66config BR2_x86_pentium_mmx 67 bool "pentium MMX" 68 depends on !BR2_x86_64 69 select BR2_X86_CPU_HAS_MMX 70config BR2_x86_pentium_m 71 bool "pentium mobile" 72 depends on !BR2_x86_64 73 select BR2_X86_CPU_HAS_MMX 74 select BR2_X86_CPU_HAS_SSE 75 select BR2_X86_CPU_HAS_SSE2 76config BR2_x86_pentium2 77 bool "pentium2" 78 depends on !BR2_x86_64 79 select BR2_X86_CPU_HAS_MMX 80config BR2_x86_pentium3 81 bool "pentium3" 82 depends on !BR2_x86_64 83 select BR2_X86_CPU_HAS_MMX 84 select BR2_X86_CPU_HAS_SSE 85config BR2_x86_pentium4 86 bool "pentium4" 87 depends on !BR2_x86_64 88 select BR2_X86_CPU_HAS_MMX 89 select BR2_X86_CPU_HAS_SSE 90 select BR2_X86_CPU_HAS_SSE2 91config BR2_x86_prescott 92 bool "prescott" 93 depends on !BR2_x86_64 94 select BR2_X86_CPU_HAS_MMX 95 select BR2_X86_CPU_HAS_SSE 96 select BR2_X86_CPU_HAS_SSE2 97 select BR2_X86_CPU_HAS_SSE3 98config BR2_x86_x86_64 99 bool "x86-64" 100 depends on BR2_x86_64 101 select BR2_X86_CPU_HAS_MMX 102 select BR2_X86_CPU_HAS_SSE 103 select BR2_X86_CPU_HAS_SSE2 104 help 105 This option corresponds to -march=x86-64, documented as a 106 "Generic CPU with 64-bit extensions" by the GCC 107 documentation. It is a 64-bit CPU with MMX, SSE and SSE2 108 support. 109config BR2_x86_x86_64_v2 110 bool "x86-64-v2" 111 depends on BR2_x86_64 112 select BR2_X86_CPU_HAS_MMX 113 select BR2_X86_CPU_HAS_SSE 114 select BR2_X86_CPU_HAS_SSE2 115 select BR2_X86_CPU_HAS_SSE3 116 select BR2_X86_CPU_HAS_SSSE3 117 select BR2_X86_CPU_HAS_SSE4 118 select BR2_X86_CPU_HAS_SSE42 119 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 120 help 121 This option corresponds to the x86-64-v2 micro-architecture 122 level, as defined by the x86-64 psABI document, see 123 https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. 124 125 It is close to the Nehalem CPU architecture, and is 126 applicable for CPUs that support CMPXCHG16B, LAHF-SAHF, 127 POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3. 128config BR2_x86_x86_64_v3 129 bool "x86-64-v3" 130 depends on BR2_x86_64 131 select BR2_X86_CPU_HAS_MMX 132 select BR2_X86_CPU_HAS_SSE 133 select BR2_X86_CPU_HAS_SSE2 134 select BR2_X86_CPU_HAS_SSE3 135 select BR2_X86_CPU_HAS_SSSE3 136 select BR2_X86_CPU_HAS_SSE4 137 select BR2_X86_CPU_HAS_SSE42 138 select BR2_X86_CPU_HAS_AVX 139 select BR2_X86_CPU_HAS_AVX2 140 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 141 help 142 This option corresponds to the x86-64-v3 micro-architecture 143 level, as defined by the x86-64 psABI document, see 144 https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. 145 146 It is close to the Haswell CPU architecture, and is 147 applicable for CPUs that support all of x86-64-v2 plus AVX, 148 AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE. 149config BR2_x86_x86_64_v4 150 bool "x86-64-v4" 151 depends on BR2_x86_64 152 select BR2_X86_CPU_HAS_MMX 153 select BR2_X86_CPU_HAS_SSE 154 select BR2_X86_CPU_HAS_SSE2 155 select BR2_X86_CPU_HAS_SSE3 156 select BR2_X86_CPU_HAS_SSSE3 157 select BR2_X86_CPU_HAS_SSE4 158 select BR2_X86_CPU_HAS_SSE42 159 select BR2_X86_CPU_HAS_AVX 160 select BR2_X86_CPU_HAS_AVX2 161 select BR2_X86_CPU_HAS_AVX512 162 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 163 help 164 This option corresponds to the x86-64-v4 micro-architecture 165 level, as defined by the x86-64 psABI document, see 166 https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. 167 168 It is applicable for CPUs that support all of x86-64-v3 plus 169 AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL. 170config BR2_x86_nocona 171 bool "nocona" 172 select BR2_X86_CPU_HAS_MMX 173 select BR2_X86_CPU_HAS_SSE 174 select BR2_X86_CPU_HAS_SSE2 175 select BR2_X86_CPU_HAS_SSE3 176config BR2_x86_core2 177 bool "core2" 178 select BR2_X86_CPU_HAS_MMX 179 select BR2_X86_CPU_HAS_SSE 180 select BR2_X86_CPU_HAS_SSE2 181 select BR2_X86_CPU_HAS_SSE3 182 select BR2_X86_CPU_HAS_SSSE3 183config BR2_x86_corei7 184 bool "corei7" 185 select BR2_X86_CPU_HAS_MMX 186 select BR2_X86_CPU_HAS_SSE 187 select BR2_X86_CPU_HAS_SSE2 188 select BR2_X86_CPU_HAS_SSE3 189 select BR2_X86_CPU_HAS_SSSE3 190 select BR2_X86_CPU_HAS_SSE4 191 select BR2_X86_CPU_HAS_SSE42 192 help 193 This option is deprecated. Since gcc 4.9, the gcc option 194 "nehalem" is preferred. Use BR2_x86_nehalem instead. 195config BR2_x86_nehalem 196 bool "nehalem" 197 select BR2_X86_CPU_HAS_MMX 198 select BR2_X86_CPU_HAS_SSE 199 select BR2_X86_CPU_HAS_SSE2 200 select BR2_X86_CPU_HAS_SSE3 201 select BR2_X86_CPU_HAS_SSSE3 202 select BR2_X86_CPU_HAS_SSE4 203 select BR2_X86_CPU_HAS_SSE42 204 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 205config BR2_x86_westmere 206 bool "westmere" 207 select BR2_X86_CPU_HAS_MMX 208 select BR2_X86_CPU_HAS_SSE 209 select BR2_X86_CPU_HAS_SSE2 210 select BR2_X86_CPU_HAS_SSE3 211 select BR2_X86_CPU_HAS_SSSE3 212 select BR2_X86_CPU_HAS_SSE4 213 select BR2_X86_CPU_HAS_SSE42 214 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 215config BR2_x86_corei7_avx 216 bool "corei7-avx" 217 select BR2_X86_CPU_HAS_MMX 218 select BR2_X86_CPU_HAS_SSE 219 select BR2_X86_CPU_HAS_SSE2 220 select BR2_X86_CPU_HAS_SSE3 221 select BR2_X86_CPU_HAS_SSSE3 222 select BR2_X86_CPU_HAS_SSE4 223 select BR2_X86_CPU_HAS_SSE42 224 select BR2_X86_CPU_HAS_AVX 225 help 226 This option is deprecated. Since gcc 4.9, the gcc option 227 "sandybridge" is preferred. Use BR2_x86_sandybridge instead. 228config BR2_x86_sandybridge 229 bool "sandybridge" 230 select BR2_X86_CPU_HAS_MMX 231 select BR2_X86_CPU_HAS_SSE 232 select BR2_X86_CPU_HAS_SSE2 233 select BR2_X86_CPU_HAS_SSE3 234 select BR2_X86_CPU_HAS_SSSE3 235 select BR2_X86_CPU_HAS_SSE4 236 select BR2_X86_CPU_HAS_SSE42 237 select BR2_X86_CPU_HAS_AVX 238 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 239config BR2_x86_ivybridge 240 bool "ivybridge" 241 select BR2_X86_CPU_HAS_MMX 242 select BR2_X86_CPU_HAS_SSE 243 select BR2_X86_CPU_HAS_SSE2 244 select BR2_X86_CPU_HAS_SSE3 245 select BR2_X86_CPU_HAS_SSSE3 246 select BR2_X86_CPU_HAS_SSE4 247 select BR2_X86_CPU_HAS_SSE42 248 select BR2_X86_CPU_HAS_AVX 249 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 250config BR2_x86_core_avx2 251 bool "core-avx2" 252 select BR2_X86_CPU_HAS_MMX 253 select BR2_X86_CPU_HAS_SSE 254 select BR2_X86_CPU_HAS_SSE2 255 select BR2_X86_CPU_HAS_SSE3 256 select BR2_X86_CPU_HAS_SSSE3 257 select BR2_X86_CPU_HAS_SSE4 258 select BR2_X86_CPU_HAS_SSE42 259 select BR2_X86_CPU_HAS_AVX 260 select BR2_X86_CPU_HAS_AVX2 261 help 262 This option is deprecated. Since gcc 4.9, the gcc option 263 "haswell" is preferred. Use BR2_x86_haswell instead. 264config BR2_x86_haswell 265 bool "haswell" 266 select BR2_X86_CPU_HAS_MMX 267 select BR2_X86_CPU_HAS_SSE 268 select BR2_X86_CPU_HAS_SSE2 269 select BR2_X86_CPU_HAS_SSE3 270 select BR2_X86_CPU_HAS_SSSE3 271 select BR2_X86_CPU_HAS_SSE4 272 select BR2_X86_CPU_HAS_SSE42 273 select BR2_X86_CPU_HAS_AVX 274 select BR2_X86_CPU_HAS_AVX2 275 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 276config BR2_x86_broadwell 277 bool "broadwell" 278 select BR2_X86_CPU_HAS_MMX 279 select BR2_X86_CPU_HAS_SSE 280 select BR2_X86_CPU_HAS_SSE2 281 select BR2_X86_CPU_HAS_SSE3 282 select BR2_X86_CPU_HAS_SSSE3 283 select BR2_X86_CPU_HAS_SSE4 284 select BR2_X86_CPU_HAS_SSE42 285 select BR2_X86_CPU_HAS_AVX 286 select BR2_X86_CPU_HAS_AVX2 287 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 288config BR2_x86_skylake 289 bool "skylake" 290 select BR2_X86_CPU_HAS_MMX 291 select BR2_X86_CPU_HAS_SSE 292 select BR2_X86_CPU_HAS_SSE2 293 select BR2_X86_CPU_HAS_SSE3 294 select BR2_X86_CPU_HAS_SSSE3 295 select BR2_X86_CPU_HAS_SSE4 296 select BR2_X86_CPU_HAS_SSE42 297 select BR2_X86_CPU_HAS_AVX 298 select BR2_X86_CPU_HAS_AVX2 299 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 300config BR2_x86_atom 301 bool "atom" 302 select BR2_X86_CPU_HAS_MMX 303 select BR2_X86_CPU_HAS_SSE 304 select BR2_X86_CPU_HAS_SSE2 305 select BR2_X86_CPU_HAS_SSE3 306 select BR2_X86_CPU_HAS_SSSE3 307 help 308 This option is deprecated. Since gcc 4.9, the gcc option 309 "bonnell" is preferred. Use BR2_x86_bonnell instead. 310config BR2_x86_bonnell 311 bool "bonnell" 312 select BR2_X86_CPU_HAS_MMX 313 select BR2_X86_CPU_HAS_SSE 314 select BR2_X86_CPU_HAS_SSE2 315 select BR2_X86_CPU_HAS_SSE3 316 select BR2_X86_CPU_HAS_SSSE3 317 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 318config BR2_x86_silvermont 319 bool "silvermont" 320 select BR2_X86_CPU_HAS_MMX 321 select BR2_X86_CPU_HAS_SSE 322 select BR2_X86_CPU_HAS_SSE2 323 select BR2_X86_CPU_HAS_SSE3 324 select BR2_X86_CPU_HAS_SSSE3 325 select BR2_X86_CPU_HAS_SSE4 326 select BR2_X86_CPU_HAS_SSE42 327 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 328config BR2_x86_goldmont 329 bool "goldmont" 330 select BR2_X86_CPU_HAS_MMX 331 select BR2_X86_CPU_HAS_SSE 332 select BR2_X86_CPU_HAS_SSE2 333 select BR2_X86_CPU_HAS_SSE3 334 select BR2_X86_CPU_HAS_SSSE3 335 select BR2_X86_CPU_HAS_SSE4 336 select BR2_X86_CPU_HAS_SSE42 337 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 338config BR2_x86_goldmont_plus 339 bool "goldmont-plus" 340 select BR2_X86_CPU_HAS_MMX 341 select BR2_X86_CPU_HAS_SSE 342 select BR2_X86_CPU_HAS_SSE2 343 select BR2_X86_CPU_HAS_SSE3 344 select BR2_X86_CPU_HAS_SSSE3 345 select BR2_X86_CPU_HAS_SSE4 346 select BR2_X86_CPU_HAS_SSE42 347 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 348config BR2_x86_tremont 349 bool "tremont" 350 select BR2_X86_CPU_HAS_MMX 351 select BR2_X86_CPU_HAS_SSE 352 select BR2_X86_CPU_HAS_SSE2 353 select BR2_X86_CPU_HAS_SSE3 354 select BR2_X86_CPU_HAS_SSSE3 355 select BR2_X86_CPU_HAS_SSE4 356 select BR2_X86_CPU_HAS_SSE42 357 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 358config BR2_x86_sierraforest 359 bool "sierraforest" 360 select BR2_X86_CPU_HAS_MMX 361 select BR2_X86_CPU_HAS_SSE 362 select BR2_X86_CPU_HAS_SSE2 363 select BR2_X86_CPU_HAS_SSE3 364 select BR2_X86_CPU_HAS_SSSE3 365 select BR2_X86_CPU_HAS_SSE4 366 select BR2_X86_CPU_HAS_SSE42 367 select BR2_X86_CPU_HAS_AVX 368 select BR2_X86_CPU_HAS_AVX2 369 select BR2_ARCH_NEEDS_GCC_AT_LEAST_13 370config BR2_x86_grandridge 371 bool "grandridge" 372 select BR2_X86_CPU_HAS_MMX 373 select BR2_X86_CPU_HAS_SSE 374 select BR2_X86_CPU_HAS_SSE2 375 select BR2_X86_CPU_HAS_SSE3 376 select BR2_X86_CPU_HAS_SSSE3 377 select BR2_X86_CPU_HAS_SSE4 378 select BR2_X86_CPU_HAS_SSE42 379 select BR2_X86_CPU_HAS_AVX 380 select BR2_X86_CPU_HAS_AVX2 381 select BR2_ARCH_NEEDS_GCC_AT_LEAST_13 382config BR2_x86_knightslanding 383 bool "knightslanding" 384 select BR2_X86_CPU_HAS_MMX 385 select BR2_X86_CPU_HAS_SSE 386 select BR2_X86_CPU_HAS_SSE2 387 select BR2_X86_CPU_HAS_SSE3 388 select BR2_X86_CPU_HAS_SSSE3 389 select BR2_X86_CPU_HAS_SSE4 390 select BR2_X86_CPU_HAS_SSE42 391 select BR2_X86_CPU_HAS_AVX 392 select BR2_X86_CPU_HAS_AVX2 393 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 394config BR2_x86_knightsmill 395 bool "knightsmill" 396 select BR2_X86_CPU_HAS_MMX 397 select BR2_X86_CPU_HAS_SSE 398 select BR2_X86_CPU_HAS_SSE2 399 select BR2_X86_CPU_HAS_SSE3 400 select BR2_X86_CPU_HAS_SSSE3 401 select BR2_X86_CPU_HAS_SSE4 402 select BR2_X86_CPU_HAS_SSE42 403 select BR2_X86_CPU_HAS_AVX 404 select BR2_X86_CPU_HAS_AVX2 405 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 406config BR2_x86_skylake_avx512 407 bool "skylake-avx512" 408 select BR2_X86_CPU_HAS_MMX 409 select BR2_X86_CPU_HAS_SSE 410 select BR2_X86_CPU_HAS_SSE2 411 select BR2_X86_CPU_HAS_SSE3 412 select BR2_X86_CPU_HAS_SSSE3 413 select BR2_X86_CPU_HAS_SSE4 414 select BR2_X86_CPU_HAS_SSE42 415 select BR2_X86_CPU_HAS_AVX 416 select BR2_X86_CPU_HAS_AVX2 417 select BR2_X86_CPU_HAS_AVX512 418 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 419config BR2_x86_cannonlake 420 bool "cannonlake" 421 select BR2_X86_CPU_HAS_MMX 422 select BR2_X86_CPU_HAS_SSE 423 select BR2_X86_CPU_HAS_SSE2 424 select BR2_X86_CPU_HAS_SSE3 425 select BR2_X86_CPU_HAS_SSSE3 426 select BR2_X86_CPU_HAS_SSE4 427 select BR2_X86_CPU_HAS_SSE42 428 select BR2_X86_CPU_HAS_AVX 429 select BR2_X86_CPU_HAS_AVX2 430 select BR2_X86_CPU_HAS_AVX512 431 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 432config BR2_x86_icelake_client 433 bool "icelake-client" 434 select BR2_X86_CPU_HAS_MMX 435 select BR2_X86_CPU_HAS_SSE 436 select BR2_X86_CPU_HAS_SSE2 437 select BR2_X86_CPU_HAS_SSE3 438 select BR2_X86_CPU_HAS_SSSE3 439 select BR2_X86_CPU_HAS_SSE4 440 select BR2_X86_CPU_HAS_SSE42 441 select BR2_X86_CPU_HAS_AVX 442 select BR2_X86_CPU_HAS_AVX2 443 select BR2_X86_CPU_HAS_AVX512 444 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 445config BR2_x86_icelake_server 446 bool "icelake-server" 447 select BR2_X86_CPU_HAS_MMX 448 select BR2_X86_CPU_HAS_SSE 449 select BR2_X86_CPU_HAS_SSE2 450 select BR2_X86_CPU_HAS_SSE3 451 select BR2_X86_CPU_HAS_SSSE3 452 select BR2_X86_CPU_HAS_SSE4 453 select BR2_X86_CPU_HAS_SSE42 454 select BR2_X86_CPU_HAS_AVX 455 select BR2_X86_CPU_HAS_AVX2 456 select BR2_X86_CPU_HAS_AVX512 457 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 458config BR2_x86_cascadelake 459 bool "cascadelake" 460 select BR2_X86_CPU_HAS_MMX 461 select BR2_X86_CPU_HAS_SSE 462 select BR2_X86_CPU_HAS_SSE2 463 select BR2_X86_CPU_HAS_SSE3 464 select BR2_X86_CPU_HAS_SSSE3 465 select BR2_X86_CPU_HAS_SSE4 466 select BR2_X86_CPU_HAS_SSE42 467 select BR2_X86_CPU_HAS_AVX 468 select BR2_X86_CPU_HAS_AVX2 469 select BR2_X86_CPU_HAS_AVX512 470 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 471config BR2_x86_cooperlake 472 bool "cooperlake" 473 select BR2_X86_CPU_HAS_MMX 474 select BR2_X86_CPU_HAS_SSE 475 select BR2_X86_CPU_HAS_SSE2 476 select BR2_X86_CPU_HAS_SSE3 477 select BR2_X86_CPU_HAS_SSSE3 478 select BR2_X86_CPU_HAS_SSE4 479 select BR2_X86_CPU_HAS_SSE42 480 select BR2_X86_CPU_HAS_AVX 481 select BR2_X86_CPU_HAS_AVX2 482 select BR2_X86_CPU_HAS_AVX512 483 select BR2_ARCH_NEEDS_GCC_AT_LEAST_10 484config BR2_x86_tigerlake 485 bool "tigerlake" 486 select BR2_X86_CPU_HAS_MMX 487 select BR2_X86_CPU_HAS_SSE 488 select BR2_X86_CPU_HAS_SSE2 489 select BR2_X86_CPU_HAS_SSE3 490 select BR2_X86_CPU_HAS_SSSE3 491 select BR2_X86_CPU_HAS_SSE4 492 select BR2_X86_CPU_HAS_SSE42 493 select BR2_X86_CPU_HAS_AVX 494 select BR2_X86_CPU_HAS_AVX2 495 select BR2_X86_CPU_HAS_AVX512 496 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 497config BR2_x86_sapphirerapids 498 bool "sapphirerapids" 499 select BR2_X86_CPU_HAS_MMX 500 select BR2_X86_CPU_HAS_SSE 501 select BR2_X86_CPU_HAS_SSE2 502 select BR2_X86_CPU_HAS_SSE3 503 select BR2_X86_CPU_HAS_SSSE3 504 select BR2_X86_CPU_HAS_SSE4 505 select BR2_X86_CPU_HAS_SSE42 506 select BR2_X86_CPU_HAS_AVX 507 select BR2_X86_CPU_HAS_AVX2 508 select BR2_X86_CPU_HAS_AVX512 509 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 510 help 511 Use for Sapphire Rapids, Emerald Rapids 512config BR2_x86_alderlake 513 bool "alderlake" 514 select BR2_X86_CPU_HAS_MMX 515 select BR2_X86_CPU_HAS_SSE 516 select BR2_X86_CPU_HAS_SSE2 517 select BR2_X86_CPU_HAS_SSE3 518 select BR2_X86_CPU_HAS_SSSE3 519 select BR2_X86_CPU_HAS_SSE4 520 select BR2_X86_CPU_HAS_SSE42 521 select BR2_X86_CPU_HAS_AVX 522 select BR2_X86_CPU_HAS_AVX2 523 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 524 help 525 Use for Alder Lake, Raptor Lake, Meteor Lake 526config BR2_x86_rocketlake 527 bool "rocketlake" 528 select BR2_X86_CPU_HAS_MMX 529 select BR2_X86_CPU_HAS_SSE 530 select BR2_X86_CPU_HAS_SSE2 531 select BR2_X86_CPU_HAS_SSE3 532 select BR2_X86_CPU_HAS_SSSE3 533 select BR2_X86_CPU_HAS_SSE4 534 select BR2_X86_CPU_HAS_SSE42 535 select BR2_X86_CPU_HAS_AVX 536 select BR2_X86_CPU_HAS_AVX2 537 select BR2_X86_CPU_HAS_AVX512 538 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 539config BR2_x86_graniterapids 540 bool "graniterapids" 541 select BR2_X86_CPU_HAS_MMX 542 select BR2_X86_CPU_HAS_SSE 543 select BR2_X86_CPU_HAS_SSE2 544 select BR2_X86_CPU_HAS_SSE3 545 select BR2_X86_CPU_HAS_SSSE3 546 select BR2_X86_CPU_HAS_SSE4 547 select BR2_X86_CPU_HAS_SSE42 548 select BR2_X86_CPU_HAS_AVX 549 select BR2_X86_CPU_HAS_AVX2 550 select BR2_X86_CPU_HAS_AVX512 551 select BR2_ARCH_NEEDS_GCC_AT_LEAST_13 552config BR2_x86_graniterapids_d 553 bool "graniterapids-d" 554 select BR2_X86_CPU_HAS_MMX 555 select BR2_X86_CPU_HAS_SSE 556 select BR2_X86_CPU_HAS_SSE2 557 select BR2_X86_CPU_HAS_SSE3 558 select BR2_X86_CPU_HAS_SSSE3 559 select BR2_X86_CPU_HAS_SSE4 560 select BR2_X86_CPU_HAS_SSE42 561 select BR2_X86_CPU_HAS_AVX 562 select BR2_X86_CPU_HAS_AVX2 563 select BR2_X86_CPU_HAS_AVX512 564 select BR2_ARCH_NEEDS_GCC_AT_LEAST_13 565config BR2_x86_k6 566 bool "k6" 567 depends on !BR2_x86_64 568 select BR2_X86_CPU_HAS_MMX 569config BR2_x86_k6_2 570 bool "k6-2" 571 depends on !BR2_x86_64 572 select BR2_X86_CPU_HAS_MMX 573 select BR2_X86_CPU_HAS_3DNOW 574config BR2_x86_athlon 575 bool "athlon" 576 depends on !BR2_x86_64 577 select BR2_X86_CPU_HAS_MMX 578 select BR2_X86_CPU_HAS_3DNOW 579config BR2_x86_athlon_4 580 bool "athlon-4" 581 depends on !BR2_x86_64 582 select BR2_X86_CPU_HAS_MMX 583 select BR2_X86_CPU_HAS_SSE 584 select BR2_X86_CPU_HAS_3DNOW 585config BR2_x86_opteron 586 bool "opteron" 587 select BR2_X86_CPU_HAS_MMX 588 select BR2_X86_CPU_HAS_SSE 589 select BR2_X86_CPU_HAS_SSE2 590config BR2_x86_opteron_sse3 591 bool "opteron w/ SSE3" 592 select BR2_X86_CPU_HAS_MMX 593 select BR2_X86_CPU_HAS_SSE 594 select BR2_X86_CPU_HAS_SSE2 595 select BR2_X86_CPU_HAS_SSE3 596config BR2_x86_barcelona 597 bool "barcelona" 598 select BR2_X86_CPU_HAS_MMX 599 select BR2_X86_CPU_HAS_SSE 600 select BR2_X86_CPU_HAS_SSE2 601 select BR2_X86_CPU_HAS_SSE3 602config BR2_x86_bobcat 603 bool "bobcat" 604 select BR2_X86_CPU_HAS_MMX 605 select BR2_X86_CPU_HAS_SSE 606 select BR2_X86_CPU_HAS_SSE2 607 select BR2_X86_CPU_HAS_SSE3 608 select BR2_X86_CPU_HAS_SSSE3 609config BR2_x86_jaguar 610 bool "jaguar" 611 select BR2_X86_CPU_HAS_MMX 612 select BR2_X86_CPU_HAS_SSE 613 select BR2_X86_CPU_HAS_SSE2 614 select BR2_X86_CPU_HAS_SSE3 615 select BR2_X86_CPU_HAS_SSSE3 616 select BR2_X86_CPU_HAS_SSE4 617 select BR2_X86_CPU_HAS_SSE42 618 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 619config BR2_x86_bulldozer 620 bool "bulldozer" 621 select BR2_X86_CPU_HAS_MMX 622 select BR2_X86_CPU_HAS_SSE 623 select BR2_X86_CPU_HAS_SSE2 624 select BR2_X86_CPU_HAS_SSE3 625 select BR2_X86_CPU_HAS_SSSE3 626 select BR2_X86_CPU_HAS_SSE4 627 select BR2_X86_CPU_HAS_SSE42 628config BR2_x86_piledriver 629 bool "piledriver" 630 select BR2_X86_CPU_HAS_MMX 631 select BR2_X86_CPU_HAS_SSE 632 select BR2_X86_CPU_HAS_SSE2 633 select BR2_X86_CPU_HAS_SSE3 634 select BR2_X86_CPU_HAS_SSSE3 635 select BR2_X86_CPU_HAS_SSE4 636 select BR2_X86_CPU_HAS_SSE42 637config BR2_x86_steamroller 638 bool "steamroller" 639 select BR2_X86_CPU_HAS_MMX 640 select BR2_X86_CPU_HAS_SSE 641 select BR2_X86_CPU_HAS_SSE2 642 select BR2_X86_CPU_HAS_SSE3 643 select BR2_X86_CPU_HAS_SSSE3 644 select BR2_X86_CPU_HAS_SSE4 645 select BR2_X86_CPU_HAS_SSE42 646 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 647config BR2_x86_excavator 648 bool "excavator" 649 select BR2_X86_CPU_HAS_MMX 650 select BR2_X86_CPU_HAS_SSE 651 select BR2_X86_CPU_HAS_SSE2 652 select BR2_X86_CPU_HAS_SSE3 653 select BR2_X86_CPU_HAS_SSSE3 654 select BR2_X86_CPU_HAS_SSE4 655 select BR2_X86_CPU_HAS_SSE42 656 select BR2_X86_CPU_HAS_AVX 657 select BR2_X86_CPU_HAS_AVX2 658 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 659config BR2_x86_zen 660 bool "zen" 661 select BR2_X86_CPU_HAS_MMX 662 select BR2_X86_CPU_HAS_SSE 663 select BR2_X86_CPU_HAS_SSE2 664 select BR2_X86_CPU_HAS_SSE3 665 select BR2_X86_CPU_HAS_SSSE3 666 select BR2_X86_CPU_HAS_SSE4 667 select BR2_X86_CPU_HAS_SSE42 668 select BR2_X86_CPU_HAS_AVX 669 select BR2_X86_CPU_HAS_AVX2 670 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 671config BR2_x86_zen2 672 bool "zen 2" 673 select BR2_X86_CPU_HAS_MMX 674 select BR2_X86_CPU_HAS_SSE 675 select BR2_X86_CPU_HAS_SSE2 676 select BR2_X86_CPU_HAS_SSE3 677 select BR2_X86_CPU_HAS_SSSE3 678 select BR2_X86_CPU_HAS_SSE4 679 select BR2_X86_CPU_HAS_SSE42 680 select BR2_X86_CPU_HAS_AVX 681 select BR2_X86_CPU_HAS_AVX2 682 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 683config BR2_x86_zen3 684 bool "zen 3" 685 select BR2_X86_CPU_HAS_MMX 686 select BR2_X86_CPU_HAS_SSE 687 select BR2_X86_CPU_HAS_SSE2 688 select BR2_X86_CPU_HAS_SSE3 689 select BR2_X86_CPU_HAS_SSSE3 690 select BR2_X86_CPU_HAS_SSE4 691 select BR2_X86_CPU_HAS_SSE42 692 select BR2_X86_CPU_HAS_AVX 693 select BR2_X86_CPU_HAS_AVX2 694 select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 695config BR2_x86_zen4 696 bool "zen 4" 697 select BR2_X86_CPU_HAS_MMX 698 select BR2_X86_CPU_HAS_SSE 699 select BR2_X86_CPU_HAS_SSE2 700 select BR2_X86_CPU_HAS_SSE3 701 select BR2_X86_CPU_HAS_SSSE3 702 select BR2_X86_CPU_HAS_SSE4 703 select BR2_X86_CPU_HAS_SSE42 704 select BR2_X86_CPU_HAS_AVX 705 select BR2_X86_CPU_HAS_AVX2 706 select BR2_X86_CPU_HAS_AVX512 707 select BR2_ARCH_NEEDS_GCC_AT_LEAST_13 708config BR2_x86_geode 709 bool "AMD Geode" 710 depends on !BR2_x86_64 711 select BR2_X86_CPU_HAS_MMX 712 select BR2_X86_CPU_HAS_3DNOW 713config BR2_x86_c3 714 bool "Via/Cyrix C3 (Samuel/Ezra cores)" 715 depends on !BR2_x86_64 716 select BR2_X86_CPU_HAS_MMX 717 select BR2_X86_CPU_HAS_3DNOW 718config BR2_x86_c32 719 bool "Via C3-2 (Nehemiah cores)" 720 depends on !BR2_x86_64 721 select BR2_X86_CPU_HAS_MMX 722 select BR2_X86_CPU_HAS_SSE 723config BR2_x86_winchip_c6 724 bool "IDT Winchip C6" 725 depends on !BR2_x86_64 726 select BR2_X86_CPU_HAS_MMX 727config BR2_x86_winchip2 728 bool "IDT Winchip 2" 729 depends on !BR2_x86_64 730 select BR2_X86_CPU_HAS_MMX 731endchoice 732 733config BR2_ARCH 734 default "i486" if BR2_x86_i486 735 default "i586" if BR2_x86_i586 736 default "i586" if BR2_x86_x1000 737 default "i586" if BR2_x86_pentium_mmx 738 default "i586" if BR2_x86_geode 739 default "i586" if BR2_x86_c3 740 default "i686" if BR2_x86_c32 741 default "i586" if BR2_x86_winchip_c6 742 default "i586" if BR2_x86_winchip2 743 # We use the property of Kconfig that the first match of a 744 # list of default will be chosen. So the following entry will 745 # not match for all BR2_i386=y configurations, but only the 746 # ones that didn't match any of the previous cases (i486, 747 # i586). 748 default "i686" if BR2_i386 749 default "x86_64" if BR2_x86_64 750 751config BR2_NORMALIZED_ARCH 752 default "i386" if !BR2_x86_64 753 default "x86_64" if BR2_x86_64 754 755config BR2_ENDIAN 756 default "LITTLE" 757 758config BR2_GCC_TARGET_ARCH 759 default "i486" if BR2_x86_i486 760 default "i586" if BR2_x86_i586 761 default "i586" if BR2_x86_x1000 762 default "pentium-mmx" if BR2_x86_pentium_mmx 763 default "i686" if BR2_x86_i686 764 default "pentiumpro" if BR2_x86_pentiumpro 765 default "pentium-m" if BR2_x86_pentium_m 766 default "pentium2" if BR2_x86_pentium2 767 default "pentium3" if BR2_x86_pentium3 768 default "pentium4" if BR2_x86_pentium4 769 default "prescott" if BR2_x86_prescott 770 default "x86-64" if BR2_x86_x86_64 771 default "x86-64-v2" if BR2_x86_x86_64_v2 772 default "x86-64-v3" if BR2_x86_x86_64_v3 773 default "x86-64-v4" if BR2_x86_x86_64_v4 774 default "nocona" if BR2_x86_nocona 775 default "core2" if BR2_x86_core2 776 default "corei7" if BR2_x86_corei7 777 default "nehalem" if BR2_x86_nehalem 778 default "corei7-avx" if BR2_x86_corei7_avx 779 default "sandybridge" if BR2_x86_sandybridge 780 default "ivybridge" if BR2_x86_ivybridge 781 default "core-avx2" if BR2_x86_core_avx2 782 default "haswell" if BR2_x86_haswell 783 default "broadwell" if BR2_x86_broadwell 784 default "skylake" if BR2_x86_skylake 785 default "atom" if BR2_x86_atom 786 default "bonnell" if BR2_x86_bonnell 787 default "westmere" if BR2_x86_westmere 788 default "silvermont" if BR2_x86_silvermont 789 default "goldmont" if BR2_x86_goldmont 790 default "goldmont-plus" if BR2_x86_goldmont_plus 791 default "tremont" if BR2_x86_tremont 792 default "sierraforest" if BR2_x86_sierraforest 793 default "grandridge" if BR2_x86_grandridge 794 default "knl" if BR2_x86_knightslanding 795 default "knm" if BR2_x86_knightsmill 796 default "skylake-avx512" if BR2_x86_skylake_avx512 797 default "cannonlake" if BR2_x86_cannonlake 798 default "icelake-client" if BR2_x86_icelake_client 799 default "icelake-server" if BR2_x86_icelake_server 800 default "cascadelake" if BR2_x86_cascadelake 801 default "cooperlake" if BR2_x86_cooperlake 802 default "tigerlake" if BR2_x86_tigerlake 803 default "sapphirerapids" if BR2_x86_sapphirerapids 804 default "alderlake" if BR2_x86_alderlake 805 default "rocketlake" if BR2_x86_rocketlake 806 default "graniterapids" if BR2_x86_graniterapids 807 default "graniterapids-d" if BR2_x86_graniterapids_d 808 default "k8" if BR2_x86_opteron 809 default "k8-sse3" if BR2_x86_opteron_sse3 810 default "barcelona" if BR2_x86_barcelona 811 default "btver1" if BR2_x86_bobcat 812 default "btver2" if BR2_x86_jaguar 813 default "bdver1" if BR2_x86_bulldozer 814 default "bdver2" if BR2_x86_piledriver 815 default "bdver3" if BR2_x86_steamroller 816 default "bdver4" if BR2_x86_excavator 817 default "znver1" if BR2_x86_zen 818 default "znver2" if BR2_x86_zen2 819 default "znver3" if BR2_x86_zen3 820 default "znver4" if BR2_x86_zen4 821 default "k6" if BR2_x86_k6 822 default "k6-2" if BR2_x86_k6_2 823 default "athlon" if BR2_x86_athlon 824 default "athlon-4" if BR2_x86_athlon_4 825 default "winchip-c6" if BR2_x86_winchip_c6 826 default "winchip2" if BR2_x86_winchip2 827 default "c3" if BR2_x86_c3 828 default "c3-2" if BR2_x86_c32 829 default "geode" if BR2_x86_geode 830 831config BR2_READELF_ARCH_NAME 832 default "Intel 80386" if BR2_i386 833 default "Advanced Micro Devices X86-64" if BR2_x86_64 834 835# vim: ft=kconfig 836# -*- mode:kconfig; -*- 837