1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd.
4 *
5 * ARMv8 Foundation model DTS
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/memreserve/ 0x80000000 0x00010000;
13
14/ {
15	model = "Foundation-v8A";
16	compatible = "arm,foundation-aarch64", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen {
22		stdout-path = "serial0:115200n8";
23	};
24
25	aliases {
26		serial0 = &v2m_serial0;
27		serial2 = &v2m_serial2;
28		serial3 = &v2m_serial3;
29	};
30
31	ftpm {
32	        compatible = "microsoft,ftpm";
33	};
34
35	cpus {
36		#address-cells = <2>;
37		#size-cells = <0>;
38
39		cpu0: cpu@0 {
40			device_type = "cpu";
41			compatible = "arm,armv8";
42			reg = <0x0 0x0>;
43			next-level-cache = <&L2_0>;
44		};
45		cpu1: cpu@1 {
46			device_type = "cpu";
47			compatible = "arm,armv8";
48			reg = <0x0 0x1>;
49			next-level-cache = <&L2_0>;
50		};
51		cpu2: cpu@2 {
52			device_type = "cpu";
53			compatible = "arm,armv8";
54			reg = <0x0 0x2>;
55			next-level-cache = <&L2_0>;
56		};
57		cpu3: cpu@3 {
58			device_type = "cpu";
59			compatible = "arm,armv8";
60			reg = <0x0 0x3>;
61			next-level-cache = <&L2_0>;
62		};
63
64		L2_0: l2-cache0 {
65			compatible = "cache";
66			cache-level = <2>;
67			cache-unified;
68		};
69	};
70
71	memory@80000000 {
72		device_type = "memory";
73		reg = <0x00000000 0x80000000 0 0x80000000>,
74		      <0x00000008 0x80000000 0 0x80000000>;
75	};
76
77	reserved-memory {
78		#address-cells = <2>;
79		#size-cells = <2>;
80		ranges;
81
82		optee@0x83000000 {
83			reg = <0x00000000 0x83000000 0 0x01000000>;
84			no-map;
85		};
86	};
87
88	timer {
89		compatible = "arm,armv8-timer";
90		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94		clock-frequency = <100000000>;
95	};
96
97	pmu {
98		compatible = "arm,armv8-pmuv3";
99		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
100			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
101			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
102			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
103	};
104
105	spe-pmu {
106		compatible = "arm,statistical-profiling-extension-v1";
107		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
108	};
109
110	watchdog@2a440000 {
111		compatible = "arm,sbsa-gwdt";
112		reg = <0x0 0x2a440000 0 0x1000>,
113			<0x0 0x2a450000 0 0x1000>;
114		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
115		timeout-sec = <30>;
116	};
117
118	v2m_clk24mhz: clock-24000000 {
119		compatible = "fixed-clock";
120		#clock-cells = <0>;
121		clock-frequency = <24000000>;
122		clock-output-names = "v2m:clk24mhz";
123	};
124
125	v2m_refclk1mhz: clock-1000000 {
126		compatible = "fixed-clock";
127		#clock-cells = <0>;
128		clock-frequency = <1000000>;
129		clock-output-names = "v2m:refclk1mhz";
130	};
131
132	v2m_refclk32khz: clock-32768 {
133		compatible = "fixed-clock";
134		#clock-cells = <0>;
135		clock-frequency = <32768>;
136		clock-output-names = "v2m:refclk32khz";
137	};
138
139	bus@8000000 {
140		compatible = "arm,vexpress,v2m-p1", "simple-bus";
141		#address-cells = <2>; /* SMB chipselect number and offset */
142		#size-cells = <1>;
143
144		ranges = <0 0 0 0x08000000 0x04000000>,
145			 <1 0 0 0x14000000 0x04000000>,
146			 <2 0 0 0x18000000 0x04000000>,
147			 <3 0 0 0x1c000000 0x04000000>,
148			 <4 0 0 0x0c000000 0x04000000>,
149			 <5 0 0 0x10000000 0x04000000>;
150
151		#interrupt-cells = <1>;
152		interrupt-map-mask = <0 0 63>;
153		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
154				<0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
155				<0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
156				<0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
157				<0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
158				<0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
159				<0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
160				<0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
161				<0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
162				<0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
163				<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
164				<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
166				<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
167				<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
168				<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
169				<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
170				<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
171				<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
172				<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
173				<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
174				<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
175				<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
176				<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
177				<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
178				<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
179				<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
180				<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
181				<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
182				<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
183				<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
184				<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
185				<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
186				<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
187				<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
188				<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
189				<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
190				<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
191				<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
192				<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
193				<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
194				<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
195				<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
196
197		ethernet@202000000 {
198			compatible = "smsc,lan91c111";
199			reg = <2 0x02000000 0x10000>;
200			interrupts = <15>;
201		};
202
203		iofpga-bus@300000000 {
204			compatible = "simple-bus";
205			#address-cells = <1>;
206			#size-cells = <1>;
207			ranges = <0 3 0 0x200000>;
208
209			v2m_sysreg: sysreg@10000 {
210				compatible = "arm,vexpress-sysreg";
211				reg = <0x010000 0x1000>;
212			};
213
214			v2m_serial0: serial@90000 {
215				compatible = "arm,pl011", "arm,primecell";
216				reg = <0x090000 0x1000>;
217				interrupts = <5>;
218				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
219				clock-names = "uartclk", "apb_pclk";
220			};
221
222			v2m_serial2: serial@b0000 {
223				compatible = "arm,pl011", "arm,primecell";
224				reg = <0x0b0000 0x1000>;
225				interrupts = <7>;
226				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
227				clock-names = "uartclk", "apb_pclk";
228			};
229
230			v2m_serial3: serial@c0000 {
231				compatible = "arm,pl011", "arm,primecell";
232				reg = <0x0c0000 0x1000>;
233				interrupts = <8>;
234				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
235				clock-names = "uartclk", "apb_pclk";
236			};
237
238			virtio@130000 {
239				compatible = "virtio,mmio";
240				reg = <0x130000 0x200>;
241				interrupts = <42>;
242			};
243		};
244	};
245
246	firmware {
247		optee {
248			compatible = "linaro,optee-tz";
249			method = "smc";
250		};
251	};
252
253};
254