1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2021 NXP 4 * 5 * Helper Code for DSPI Controller driver 6 */ 7 8 #ifndef __DRIVERS_LS_DSPI_H 9 #define __DRIVERS_LS_DSPI_H 10 11 #include <mm/core_memprot.h> 12 #include <spi.h> 13 14 /* Clock and transfer attributes */ 15 #define DSPI_CTAR_BRD 0x80000000 /* Double Baud Rate [0] */ 16 #define DSPI_CTAR_FMSZ(x) (((x) & 0x0F) << 27) /* Frame Size [1-4] */ 17 #define DSPI_CTAR_CPOL 0x04000000 /* Clock Polarity [5] */ 18 #define DSPI_CTAR_CPHA 0x02000000 /* Clock Phase [6] */ 19 #define DSPI_CTAR_LSBFE 0x01000000 /* LSB First [7] */ 20 #define DSPI_CTAR_PCS_SCK(x) (((x) & 0x03) << 22) /* PCSSCK [8-9] */ 21 #define DSPI_CTAR_PA_SCK(x) (((x) & 0x03) << 20) /* PASC [10-11] */ 22 #define DSPI_CTAR_P_DT(x) (((x) & 0x03) << 18) /* PDT [12-13] */ 23 #define DSPI_CTAR_BRP(x) \ 24 (((x) & 0x03) << 16) /* Baud Rate Prescaler [14-15] */ 25 #define DSPI_CTAR_CS_SCK(x) (((x) & 0x0F) << 12) /* CSSCK [16-19] */ 26 #define DSPI_CTAR_A_SCK(x) (((x) & 0x0F) << 8) /* ASC [20-23] */ 27 #define DSPI_CTAR_A_DT(x) (((x) & 0x0F) << 4) /* DT [24-27] */ 28 #define DSPI_CTAR_BR(x) ((x) & 0x0F) /* Baud Rate Scaler [28-31] */ 29 30 /* SPI mode flags */ 31 #define SPI_CPHA BIT(0) /* clock phase */ 32 #define SPI_CPOL BIT(1) /* clock polarity */ 33 #define SPI_CS_HIGH BIT(2) /* CS active high */ 34 #define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ 35 #define SPI_CONT BIT(4) /* Continuous CS mode */ 36 37 /* 38 * struct ls_dspi_data describes DSPI controller chip instance 39 * The structure contains below members: 40 * chip: generic spi_chip instance 41 * base: DSPI controller base address 42 * bus_clk_hz: DSPI input clk frequency 43 * speed_hz: Default SCK frequency=1mhz 44 * num_chipselect: chip/slave selection 45 * slave_bus: bus value of slave 46 * slave_cs: chip slect value of slave 47 * slave_speed_max_hz: max spped of slave 48 * slave_mode: mode of slave 49 * slave_data_size_bits:Data size to be transferred (8 or 16 bits) 50 * ctar_val: value of Clock and Transfer Attributes Register (CTAR) 51 * ctar_sel: CTAR0 or CTAR1 52 */ 53 struct ls_dspi_data { 54 struct spi_chip chip; 55 vaddr_t base; 56 unsigned int bus_clk_hz; 57 unsigned int speed_hz; 58 unsigned int num_chipselect; 59 unsigned int slave_bus; 60 unsigned int slave_cs; 61 unsigned int slave_speed_max_hz; 62 unsigned int slave_mode; 63 unsigned int slave_data_size_bits; 64 unsigned int ctar_val; 65 unsigned int ctar_sel; 66 }; 67 68 /* 69 * Initialize DSPI Controller 70 * dspi_data: DSPI controller chip instance 71 */ 72 TEE_Result ls_dspi_init(struct ls_dspi_data *dspi_data); 73 74 #endif /* __DRIVERS_LS_DSPI_H */ 75