1 /*
2 * Aspeed SD Host Controller
3 * Eddie James <eajames@linux.ibm.com>
4 *
5 * Copyright (C) 2019 IBM Corp
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qemu/error-report.h"
12 #include "hw/sd/aspeed_sdhci.h"
13 #include "qapi/error.h"
14 #include "hw/irq.h"
15 #include "migration/vmstate.h"
16 #include "hw/qdev-properties.h"
17 #include "trace.h"
18
19 #define ASPEED_SDHCI_INFO 0x00
20 #define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)
21 #define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)
22 #define ASPEED_SDHCI_INFO_RESET (1 << 0)
23 #define ASPEED_SDHCI_DEBOUNCE 0x04
24 #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
25 #define ASPEED_SDHCI_BUS 0x08
26 #define ASPEED_SDHCI_SDIO_140 0x10
27 #define ASPEED_SDHCI_SDIO_144 0x14
28 #define ASPEED_SDHCI_SDIO_148 0x18
29 #define ASPEED_SDHCI_SDIO_240 0x20
30 #define ASPEED_SDHCI_SDIO_244 0x24
31 #define ASPEED_SDHCI_SDIO_248 0x28
32 #define ASPEED_SDHCI_WP_POL 0xec
33 #define ASPEED_SDHCI_CARD_DET 0xf0
34 #define ASPEED_SDHCI_IRQ_STAT 0xfc
35
36 #define TO_REG(addr) ((addr) / sizeof(uint32_t))
37
aspeed_sdhci_read(void * opaque,hwaddr addr,unsigned int size)38 static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
39 {
40 uint64_t val = 0;
41 AspeedSDHCIState *sdhci = opaque;
42
43 switch (addr) {
44 case ASPEED_SDHCI_SDIO_140:
45 val = extract64(sdhci->slots[0].capareg, 0, 32);
46 break;
47 case ASPEED_SDHCI_SDIO_144:
48 val = extract64(sdhci->slots[0].capareg, 32, 32);
49 break;
50 case ASPEED_SDHCI_SDIO_148:
51 val = extract64(sdhci->slots[0].maxcurr, 0, 32);
52 break;
53 case ASPEED_SDHCI_SDIO_240:
54 val = extract64(sdhci->slots[1].capareg, 0, 32);
55 break;
56 case ASPEED_SDHCI_SDIO_244:
57 val = extract64(sdhci->slots[1].capareg, 32, 32);
58 break;
59 case ASPEED_SDHCI_SDIO_248:
60 val = extract64(sdhci->slots[1].maxcurr, 0, 32);
61 break;
62 default:
63 if (addr < ASPEED_SDHCI_REG_SIZE) {
64 val = sdhci->regs[TO_REG(addr)];
65 } else {
66 qemu_log_mask(LOG_GUEST_ERROR,
67 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
68 __func__, addr);
69 }
70 }
71
72 trace_aspeed_sdhci_read(addr, size, val);
73
74 return val;
75 }
76
aspeed_sdhci_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)77 static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
78 unsigned int size)
79 {
80 AspeedSDHCIState *sdhci = opaque;
81
82 trace_aspeed_sdhci_write(addr, size, val);
83
84 switch (addr) {
85 case ASPEED_SDHCI_INFO:
86 /* The RESET bit automatically clears. */
87 sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
88 break;
89 case ASPEED_SDHCI_SDIO_140:
90 sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 0, 32, val);
91 break;
92 case ASPEED_SDHCI_SDIO_144:
93 sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 32, 32, val);
94 break;
95 case ASPEED_SDHCI_SDIO_148:
96 sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr,
97 0, 32, val);
98 break;
99 case ASPEED_SDHCI_SDIO_240:
100 sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,
101 0, 32, val);
102 break;
103 case ASPEED_SDHCI_SDIO_244:
104 sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,
105 32, 32, val);
106 break;
107 case ASPEED_SDHCI_SDIO_248:
108 sdhci->slots[1].maxcurr = deposit64(sdhci->slots[0].maxcurr,
109 0, 32, val);
110 break;
111 default:
112 if (addr < ASPEED_SDHCI_REG_SIZE) {
113 sdhci->regs[TO_REG(addr)] = (uint32_t)val;
114 } else {
115 qemu_log_mask(LOG_GUEST_ERROR,
116 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
117 __func__, addr);
118 }
119 }
120 }
121
122 static const MemoryRegionOps aspeed_sdhci_ops = {
123 .read = aspeed_sdhci_read,
124 .write = aspeed_sdhci_write,
125 .endianness = DEVICE_NATIVE_ENDIAN,
126 .valid.min_access_size = 4,
127 .valid.max_access_size = 4,
128 };
129
aspeed_sdhci_set_irq(void * opaque,int n,int level)130 static void aspeed_sdhci_set_irq(void *opaque, int n, int level)
131 {
132 AspeedSDHCIState *sdhci = opaque;
133
134 if (level) {
135 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);
136
137 qemu_irq_raise(sdhci->irq);
138 } else {
139 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);
140
141 qemu_irq_lower(sdhci->irq);
142 }
143 }
144
aspeed_sdhci_realize(DeviceState * dev,Error ** errp)145 static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
146 {
147 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
148 AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
149
150 /* Create input irqs for the slots */
151 qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
152 sdhci, NULL, sdhci->num_slots);
153
154 sysbus_init_irq(sbd, &sdhci->irq);
155 memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
156 sdhci, TYPE_ASPEED_SDHCI, 0x1000);
157 sysbus_init_mmio(sbd, &sdhci->iomem);
158
159 for (int i = 0; i < sdhci->num_slots; ++i) {
160 Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
161 SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
162
163 if (!object_property_set_int(sdhci_slot, "sd-spec-version", 2, errp)) {
164 return;
165 }
166
167 if (!object_property_set_uint(sdhci_slot, "capareg",
168 ASPEED_SDHCI_CAPABILITIES, errp)) {
169 return;
170 }
171
172 if (!sysbus_realize(sbd_slot, errp)) {
173 return;
174 }
175
176 sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));
177 memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,
178 &sdhci->slots[i].iomem);
179 }
180 }
181
aspeed_sdhci_reset(DeviceState * dev)182 static void aspeed_sdhci_reset(DeviceState *dev)
183 {
184 AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
185
186 memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
187
188 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;
189 if (sdhci->num_slots == 2) {
190 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;
191 }
192 sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
193 }
194
195 static const VMStateDescription vmstate_aspeed_sdhci = {
196 .name = TYPE_ASPEED_SDHCI,
197 .version_id = 1,
198 .fields = (const VMStateField[]) {
199 VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),
200 VMSTATE_END_OF_LIST(),
201 },
202 };
203
204 static Property aspeed_sdhci_properties[] = {
205 DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
206 DEFINE_PROP_END_OF_LIST(),
207 };
208
aspeed_sdhci_class_init(ObjectClass * classp,void * data)209 static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
210 {
211 DeviceClass *dc = DEVICE_CLASS(classp);
212
213 dc->realize = aspeed_sdhci_realize;
214 device_class_set_legacy_reset(dc, aspeed_sdhci_reset);
215 dc->vmsd = &vmstate_aspeed_sdhci;
216 device_class_set_props(dc, aspeed_sdhci_properties);
217 }
218
219 static const TypeInfo aspeed_sdhci_types[] = {
220 {
221 .name = TYPE_ASPEED_SDHCI,
222 .parent = TYPE_SYS_BUS_DEVICE,
223 .instance_size = sizeof(AspeedSDHCIState),
224 .class_init = aspeed_sdhci_class_init,
225 },
226 };
227
228 DEFINE_TYPES(aspeed_sdhci_types)
229