1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36.. _arm_cpu_macros_errata_workarounds: 37 38CPU Errata Workarounds 39---------------------- 40 41TF-A exports a series of build flags which control the errata workarounds that 42are applied to each CPU by the reset handler. The errata details can be found 43in the CPU specific errata documents published by Arm: 44 45- `Cortex-A53 MPCore Software Developers Errata Notice`_ 46- `Cortex-A57 MPCore Software Developers Errata Notice`_ 47- `Cortex-A72 MPCore Software Developers Errata Notice`_ 48 49The errata workarounds are implemented for a particular revision or a set of 50processor revisions. This is checked by the reset handler at runtime. Each 51errata workaround is identified by its ``ID`` as specified in the processor's 52errata notice document. The format of the define used to enable/disable the 53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 54is for example ``A57`` for the ``Cortex_A57`` CPU. 55 56Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 57write errata workaround functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 121 ``A53_DISABLE_NON_TEMPORAL_HINT``. 122 123- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 124 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 125 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 126 which are 4kB aligned. 127 128- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 129 CPUs. Though the erratum is present in every revision of the CPU, 130 this workaround is only applied to CPUs from r0p3 onwards, which feature 131 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 132 Earlier revisions of the CPU have other errata which require the same 133 workaround in software, so they should be covered anyway. 134 135- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 136 revisions of Cortex-A53 CPU. 137 138For Cortex-A55, the following errata build flags are defined : 139 140- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 141 CPU. This needs to be enabled only for revision r0p0 of the CPU. 142 143- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 144 CPU. This needs to be enabled only for revision r0p0 of the CPU. 145 146- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 151 152- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 154 155- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 157 158- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 159 revisions of Cortex-A55 CPU. 160 161For Cortex-A57, the following errata build flags are defined : 162 163- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 164 CPU. This needs to be enabled only for revision r0p0 of the CPU. 165 166- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 167 CPU. This needs to be enabled only for revision r0p0 of the CPU. 168 169- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 177 178- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 180 181- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 183 184- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 189 190- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 192 193- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 195 196- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 197 revisions of Cortex-A57 CPU. 198 199For Cortex-A72, the following errata build flags are defined : 200 201- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 202 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 203 204- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 205 revisions of Cortex-A72 CPU. 206 207For Cortex-A73, the following errata build flags are defined : 208 209- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 210 CPU. This needs to be enabled only for revision r0p0 of the CPU. 211 212- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 213 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 214 215For Cortex-A75, the following errata build flags are defined : 216 217- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 218 CPU. This needs to be enabled only for revision r0p0 of the CPU. 219 220- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 221 CPU. This needs to be enabled only for revision r0p0 of the CPU. 222 223For Cortex-A76, the following errata build flags are defined : 224 225- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 226 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 227 228- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 229 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 230 231- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 232 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 233 234- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 236 237- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 239 240- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 242 243- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 248 249- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 250 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 251 limitation of errata framework this errata is applied to all revisions 252 of Cortex-A76 CPU. 253 254- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 255 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 256 257- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 258 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 259 260- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 261 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 262 still open. 263 264For Cortex-A77, the following errata build flags are defined : 265 266- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 267 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 268 269- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 270 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 271 272- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 273 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 274 275- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 276 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 277 278- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 279 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 280 281 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 282 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 283 284 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 286 287For Cortex-A78, the following errata build flags are defined : 288 289- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 290 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 291 292- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 293 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 294 295- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 296 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 297 issue but there is no workaround for that revision. 298 299- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 300 CPU. This needs to be enabled for revisions r0p0 and r1p0. 301 302- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 303 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 304 305- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 306 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 307 is still open. 308 309- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 310 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 311 is present in r0p0 but there is no workaround. It is still open. 312 313- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 314 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 315 it is still open. 316 317- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 318 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 319 it is still open. 320 321- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 322 CPU, this erratum affects system configurations that do not use an ARM 323 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 324 and r1p2 and it is still open. 325 326- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 327 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 328 it is still open. 329 330- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 331 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 332 it is still open. 333 334- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 335 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 336 it is still open. 337 338For Cortex-A78AE, the following errata build flags are defined : 339 340- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 341 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 342 This erratum is still open. 343 344- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 345 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 346 erratum is still open. 347 348- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 349 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 350 This erratum is still open. 351 352- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 353 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 354 erratum is still open. 355 356- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 357 Cortex-A78AE CPU. This erratum affects system configurations that do not use 358 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 359 r0p2. This erratum is still open. 360 361For Cortex-A78C, the following errata build flags are defined : 362 363- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 364 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 365 fixed in r0p1. 366 367- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 368 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 369 fixed in r0p1. 370 371- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 372 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 373 it is still open. 374 375- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 376 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 377 it is still open. 378 379- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 380 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 381 erratum is still open. 382 383- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 384 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 385 erratum is still open. 386 387- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 388 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 389 erratum is still open. 390 391- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 392 Cortex-A78C CPU, this erratum affects system configurations that do not use 393 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 394 and is still open. 395 396- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 397 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 398 This erratum is still open. 399 400- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 401 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 402 This erratum is still open. 403 404- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 405 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 406 This erratum is still open. 407 408For Cortex-X1 CPU, the following errata build flags are defined: 409 410- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 411 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 412 413- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 414 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 415 416- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 417 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 418 419For Neoverse N1, the following errata build flags are defined : 420 421- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 422 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 423 424- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 425 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 426 427- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 428 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 429 430- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 431 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 432 433- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 434 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 435 436- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 437 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 438 439- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 440 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 441 442- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 443 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 444 445- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 446 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 447 448- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 449 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 450 451- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 452 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 453 454- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 455 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 456 457- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 458 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 459 revisions r0p0, r1p0, and r2p0 there is no workaround. 460 461- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 462 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 463 still open. 464 465For Neoverse V1, the following errata build flags are defined : 466 467- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 468 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 469 r1p0. 470 471- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 472 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 473 in r1p1. 474 475- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 476 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 477 in r1p1. 478 479- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 480 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 481 in r1p1. 482 483- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 484 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 485 486- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 487 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 488 CPU. 489 490- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 491 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 492 issue is present in r0p0 as well but there is no workaround for that 493 revision. It is still open. 494 495- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 496 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 497 CPU. It is still open. 498 499- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 500 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 501 It is still open. 502 503- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 504 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 505 issue is present in r0p0 as well but there is no workaround for that 506 revision. It is still open. 507 508- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 509 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 510 the CPU. 511 512- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 513 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 514 It has been fixed in r1p2. 515 516- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 517 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 518 It is still open. 519 520- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 521 CPU, this erratum affects system configurations that do not use an ARM 522 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 523 It has been fixed in r1p2. 524 525- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 526 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 527 CPU. It is still open. 528 529- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 530 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 531 CPU. It is still open. 532 533- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 534 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 535 CPU. It is still open. 536 537For Neoverse V2, the following errata build flags are defined : 538 539- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 540 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still 541 open. 542 543- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 544 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 545 r0p2. 546 547- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 548 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 549 r0p2. 550 551- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 552 CPU, this affects system configurations that do not use and ARM interconnect 553 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 554 in r0p2. 555 556- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 557 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 558 r0p2. 559 560- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 561 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 562 r0p2. 563 564- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 565 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 566 r0p2. 567 568- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 569 CPU, this affects all configurations. This needs to be enabled for revisions 570 r0p0 and r0p1. It has been fixed in r0p2. 571 572For Cortex-A710, the following errata build flags are defined : 573 574- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 575 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 576 r2p0 of the CPU. It is still open. 577 578- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 579 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 580 r2p0 of the CPU. It is still open. 581 582- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 583 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 584 and is still open. 585 586- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 587 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 588 of the CPU and is still open. 589 590- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 591 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 592 is still open. 593 594- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 595 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 596 and r2p1 of the CPU and is still open. 597 598- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 599 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 600 of the CPU and is fixed in r2p1. 601 602- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 603 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 604 of the CPU and is fixed in r2p1. 605 606- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 607 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 608 and is fixed in r2p1. 609 610- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 611 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 612 of the CPU and is fixed in r2p1. 613 614- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 615 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 616 r2p1 of the CPU and is still open. 617 618- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 619 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 620 of the CPU and is fixed in r2p1. 621 622- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 623 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 624 of the CPU and is fixed in r2p1. 625 626- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 627 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 628 of the CPU and is fixed in r2p1. 629 630- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 631 CPU, and applies to system configurations that do not use and ARM 632 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 633 is still open. 634 635- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 636 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 637 r2p1 of the CPU and is still open. 638 639- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 640 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 641 r2p1 of the CPU and is still open. 642 643- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 644 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 645 CPU and is still open. 646 647For Neoverse N2, the following errata build flags are defined : 648 649- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 650 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 651 652- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 653 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 654 655- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 656 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 657 658- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 659 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 660 661- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 662 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 663 664- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 665 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 666 667- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 668 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 669 670- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 671 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 672 673- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 674 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 675 676- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 677 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 678 679- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 680 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 681 682- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 683 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 684 r0p1. 685 686- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 687 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 688 r0p1. 689 690- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 691 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 692 it is fixed in r0p3. 693 694- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 695 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 696 697- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 698 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 699 r0p1. 700 701- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 702 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 703 in r0p3. 704 705- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 706 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 707 in r0p3. 708 709- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 710 CPU, this erratum affects system configurations that do not use and ARM 711 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 712 It is fixed in r0p3. 713 714- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 715 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 716 in r0p3. 717 718For Cortex-X2, the following errata build flags are defined : 719 720- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 721 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 722 it is still open. 723 724- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 725 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, 726 it is still open. 727 728- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 729 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 730 731- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 732 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 733 CPU, it is fixed in r2p1. 734 735- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 736 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 737 CPU, it is fixed in r2p1. 738 739- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 740 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 741 CPU, it is fixed in r2p1. 742 743- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 744 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 745 in r2p1. 746 747- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 748 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 749 CPU and is still open. 750 751- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 752 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 753 and is fixed in r2p1. 754 755- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 756 CPU and affects system configurations that do not use an ARM interconnect IP. 757 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 758 still open. 759 760- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 761 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 762 CPU and is still open. 763 764- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 765 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 766 CPU and is still open. 767 768- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 769 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 770 CPU and it is still open. 771 772For Cortex-X3, the following errata build flags are defined : 773 774- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 775 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of 776 the CPU and is still open. 777 778- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 779 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 780 is fixed in r1p1. 781 782- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 783 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 784 fixed in r1p2. 785 786- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 787 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 788 of the CPU, it is fixed in r1p1. 789 790- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 791 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 792 of the CPU, it is fixed in r1p1. 793 794- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 795 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 796 CPU, it is fixed in r1p2. 797 798- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 799 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 800 It is fixed in r1p1. 801 802- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 803 CPU and affects system configurations that do not use an ARM interconnect 804 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 805 in r1p2. 806 807- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 808 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 809 r1p1. It is fixed in r1p2. 810 811- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 812 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 813 fixed in r1p2. 814 815- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 816 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 817 CPU. It is fixed in r1p2. 818 819For Cortex-X4, the following errata build flags are defined : 820 821- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 822 CPU and affects system configurations that do not use an Arm interconnect IP. 823 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 824 The workaround for this erratum is not implemented in EL3, but the flag can 825 be enabled/disabled at the platform level. The flag is used when the errata ABI 826 feature is enabled and can assist the Kernel in the process of 827 mitigation of the erratum. 828 829- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 830 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 831 r0p2. 832 833- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 834 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 835 in r0p2. 836 837- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 838 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 839 840- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 841 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 842 843- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 844 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 845 846- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 847 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 848 849For Cortex-A510, the following errata build flags are defined : 850 851- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 852 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 853 fixed in r0p1. 854 855- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 856 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 857 r0p2, r0p3 and r1p0, it is fixed in r1p1. 858 859- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 860 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 861 r0p2, it is fixed in r0p3. 862 863- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 864 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 865 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 866 workaround for those revisions. 867 868- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 869 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 870 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 871 workaround for those revisions. 872 873- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 874 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 875 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 876 ENABLE_MPMM=1. 877 878- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 879 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 880 r0p3 and r1p0, it is fixed in r1p1. 881 882- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 883 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 884 r0p3 and r1p0, it is fixed in r1p1. 885 886- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 887 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 888 r0p3, r1p0 and r1p1. It is fixed in r1p2. 889 890- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 891 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 892 r0p3, r1p0, r1p1, and is fixed in r1p2. 893 894- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 895 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 896 r0p3, r1p0, r1p1. It is fixed in r1p2. 897 898- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 899 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 900 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 901 902For Cortex-A520, the following errata build flags are defined : 903 904- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 905 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 906 CPU and is still open. 907 908- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 909 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 910 It is still open. 911 912- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 913 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 914 It is fixed in r0p2. 915 916For Cortex-A715, the following errata build flags are defined : 917 918- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 919 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 920 It is fixed in r1p1. 921 922- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 923 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 924 fixed in r1p1. 925 926- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 927 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 928 when SPE(Statistical profiling extension)=True. The errata is fixed 929 in r1p1. 930 931- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 932 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 933 It is fixed in r1p1. 934 935- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 936 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 937 workaround for revision r0p0. It is fixed in r1p1. 938 939- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 940 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 941 It is fixed in r1p1. 942 943- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 944 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 945 and r1p1. It is fixed in r1p2. 946 947For Cortex-A720, the following errata build flags are defined : 948 949- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 950 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 951 It is fixed in r0p2. 952 953- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 954 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 955 It is fixed in r0p2. 956 957- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 958 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 959 It is fixed in r0p2. 960 961- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 962 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 963 It is fixed in r0p2. 964 965DSU Errata Workarounds 966---------------------- 967 968Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 969Shared Unit) errata. The DSU errata details can be found in the respective Arm 970documentation: 971 972- `Arm DSU Software Developers Errata Notice`_. 973 974Each erratum is identified by an ``ID``, as defined in the DSU errata notice 975document. Thus, the build flags which enable/disable the errata workarounds 976have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 977of DSU errata workarounds are similar to `CPU errata workarounds`_. 978 979For DSU errata, the following build flags are defined: 980 981- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 982 affected DSU configurations. This errata applies only for those DSUs that 983 revision is r0p0 (on r0p1 it is fixed). However, please note that this 984 workaround results in increased DSU power consumption on idle. 985 986- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 987 affected DSU configurations. This errata applies only for those DSUs that 988 contain the ACP interface **and** the DSU revision is older than r2p0 (on 989 r2p0 it is fixed). However, please note that this workaround results in 990 increased DSU power consumption on idle. 991 992- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 993 affected DSU configurations. This errata applies for those DSUs with 994 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 995 please note that this workaround results in increased DSU power consumption 996 on idle. 997 998CPU Specific optimizations 999-------------------------- 1000 1001This section describes some of the optimizations allowed by the CPU micro 1002architecture that can be enabled by the platform as desired. 1003 1004- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1005 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1006 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1007 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1008 is a known safe deviation from the Cortex-A57 TRM defined power down 1009 sequence. Each Cortex-A57 based platform must make its own decision on 1010 whether to use the optimization. 1011 1012- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1013 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1014 in a way most programmers expect, and will most probably result in a 1015 significant speed degradation to any code that employs them. The Armv8-A 1016 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1017 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1018 flag enforces this behaviour. This needs to be enabled only for revisions 1019 <= r0p3 of the CPU and is enabled by default. 1020 1021- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1022 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1023 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1024 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1025 `Cortex-A57 Software Optimization Guide`_. 1026 1027- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1028 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1029 this bit only if their memory system meets the requirement that cache 1030 line fill requests from the Cortex-A57 processor are atomic. Each 1031 Cortex-A57 based platform must make its own decision on whether to use 1032 the optimization. This flag is disabled by default. 1033 1034- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1035 level cache(LLC) is present in the system, and that the DataSource field 1036 on the master CHI interface indicates when data is returned from the LLC. 1037 This is used to control how the LL_CACHE* PMU events count. 1038 Default value is 0 (Disabled). 1039 1040GIC Errata Workarounds 1041---------------------- 1042- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1043 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1044 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1045 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1046 then this flag is enabled; otherwise, it is 0 (Disabled). 1047 1048-------------- 1049 1050*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.* 1051 1052.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1053.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1054.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1055.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 1056.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 1057.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 1058.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 1059.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 1060