1/*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/* Configuration: 1 cluster with up to 4 CPUs */
8
9/dts-v1/;
10
11#define	AFF
12#define	CLUSTER_COUNT	1
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include "fvp-defs.dtsi"
16
17/memreserve/ 0x80000000 0x00010000;
18
19/ {
20};
21
22/ {
23	model = "FVP Foundation";
24	compatible = "arm,fvp-base", "arm,vexpress";
25	interrupt-parent = <&gic>;
26	#address-cells = <2>;
27	#size-cells = <2>;
28
29	chosen {
30		stdout-path = "serial0:115200n8";
31	};
32
33	aliases {
34		serial0 = &v2m_serial0;
35		serial1 = &v2m_serial1;
36		serial2 = &v2m_serial2;
37		serial3 = &v2m_serial3;
38	};
39
40	psci {
41		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
42		method = "smc";
43		cpu_suspend = <0xc4000001>;
44		cpu_off = <0x84000002>;
45		cpu_on = <0xc4000003>;
46		sys_poweroff = <0x84000008>;
47		sys_reset = <0x84000009>;
48		max-pwr-lvl = <2>;
49	};
50
51	cpus {
52		#address-cells = <2>;
53		#size-cells = <0>;
54
55		CPU_MAP
56
57		idle-states {
58			entry-method = "arm,psci";
59
60			CPU_SLEEP_0: cpu-sleep-0 {
61				compatible = "arm,idle-state";
62				local-timer-stop;
63				arm,psci-suspend-param = <0x0010000>;
64				entry-latency-us = <40>;
65				exit-latency-us = <100>;
66				min-residency-us = <150>;
67			};
68
69			CLUSTER_SLEEP_0: cluster-sleep-0 {
70				compatible = "arm,idle-state";
71				local-timer-stop;
72				arm,psci-suspend-param = <0x1010000>;
73				entry-latency-us = <500>;
74				exit-latency-us = <1000>;
75				min-residency-us = <2500>;
76			};
77		};
78
79		CPUS
80
81		L2_0: l2-cache0 {
82			compatible = "cache";
83		};
84	};
85
86	memory@80000000 {
87		device_type = "memory";
88		reg = <0x00000000 0x80000000 0 0x7F000000>,
89		      <0x00000008 0x80000000 0 0x80000000>;
90	};
91
92	gic: interrupt-controller@2f000000 {
93		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
94		#interrupt-cells = <3>;
95		#address-cells = <0>;
96		interrupt-controller;
97		reg = <0x0 0x2f000000 0 0x10000>,
98		      <0x0 0x2c000000 0 0x2000>,
99		      <0x0 0x2c010000 0 0x2000>,
100		      <0x0 0x2c02F000 0 0x2000>;
101		interrupts = <1 9 0xf04>;
102	};
103
104	timer {
105		compatible = "arm,armv8-timer";
106		interrupts = <GIC_PPI 13
107				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
108			     <GIC_PPI 14
109				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
110			     <GIC_PPI 11
111				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
112			     <GIC_PPI 10
113				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
114		clock-frequency = <100000000>;
115	};
116
117	timer@2a810000 {
118			compatible = "arm,armv7-timer-mem";
119			reg = <0x0 0x2a810000 0x0 0x10000>;
120			clock-frequency = <100000000>;
121			#address-cells = <2>;
122			#size-cells = <2>;
123			ranges;
124			frame@2a830000 {
125				frame-number = <1>;
126				interrupts = <0 26 4>;
127				reg = <0x0 0x2a830000 0x0 0x10000>;
128			};
129	};
130
131	pmu {
132		compatible = "arm,armv8-pmuv3";
133		interrupts = <0 60 4>,
134			     <0 61 4>,
135			     <0 62 4>,
136			     <0 63 4>;
137	};
138
139	smb {
140		compatible = "simple-bus";
141
142		#address-cells = <2>;
143		#size-cells = <1>;
144		ranges = <0 0 0 0x08000000 0x04000000>,
145			 <1 0 0 0x14000000 0x04000000>,
146			 <2 0 0 0x18000000 0x04000000>,
147			 <3 0 0 0x1c000000 0x04000000>,
148			 <4 0 0 0x0c000000 0x04000000>,
149			 <5 0 0 0x10000000 0x04000000>;
150
151		#include "fvp-foundation-motherboard.dtsi"
152	};
153};
154