1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
4 * Copyright (C) 2022 DH electronics GmbH
5 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
6 */
7
8#include "stm32mp15-pinctrl.dtsi"
9#include "stm32mp15xxaa-pinctrl.dtsi"
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
11#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
12
13/ {
14	memory@c0000000 {
15		device_type = "memory";
16		reg = <0xC0000000 0x40000000>;
17	};
18};
19
20&bsec {
21	board_id: board-id@ec {
22		reg = <0xec 0x4>;
23		st,non-secure-otp;
24	};
25};
26
27&cpu0 {
28	cpu-supply = <&vddcore>;
29};
30
31&cpu1 {
32	cpu-supply = <&vddcore>;
33};
34
35&hash1 {
36	status = "okay";
37};
38
39&i2c4 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&i2c4_pins_a>;
42	i2c-scl-rising-time-ns = <185>;
43	i2c-scl-falling-time-ns = <20>;
44	status = "okay";
45
46	pmic: stpmic@33 {
47		compatible = "st,stpmic1";
48		reg = <0x33>;
49		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
50		interrupt-controller;
51		#interrupt-cells = <2>;
52		status = "okay";
53
54		regulators {
55			compatible = "st,stpmic1-regulators";
56			ldo1-supply = <&v3v3>;
57			ldo2-supply = <&v3v3>;
58			ldo3-supply = <&vdd_ddr>;
59			ldo5-supply = <&v3v3>;
60			ldo6-supply = <&v3v3>;
61			pwr_sw1-supply = <&bst_out>;
62			pwr_sw2-supply = <&bst_out>;
63
64			vddcore: buck1 {
65				regulator-name = "vddcore";
66				regulator-min-microvolt = <1200000>;
67				regulator-max-microvolt = <1350000>;
68				regulator-always-on;
69				regulator-initial-mode = <0>;
70				regulator-over-current-protection;
71			};
72
73			vdd_ddr: buck2 {
74				regulator-name = "vdd_ddr";
75				regulator-min-microvolt = <1350000>;
76				regulator-max-microvolt = <1350000>;
77				regulator-always-on;
78				regulator-initial-mode = <0>;
79				regulator-over-current-protection;
80			};
81
82			vdd: buck3 {
83				regulator-name = "vdd";
84				regulator-min-microvolt = <3300000>;
85				regulator-max-microvolt = <3300000>;
86				regulator-always-on;
87				st,mask-reset;
88				regulator-initial-mode = <0>;
89				regulator-over-current-protection;
90			};
91
92			v3v3: buck4 {
93				regulator-name = "v3v3";
94				regulator-min-microvolt = <3300000>;
95				regulator-max-microvolt = <3300000>;
96				regulator-always-on;
97				regulator-over-current-protection;
98				regulator-initial-mode = <0>;
99			};
100
101			vdda: ldo1 {
102				regulator-name = "vdda";
103				regulator-min-microvolt = <2900000>;
104				regulator-max-microvolt = <2900000>;
105				regulator-always-on;
106			};
107
108			v2v8: ldo2 {
109				regulator-name = "v2v8";
110				regulator-min-microvolt = <2800000>;
111				regulator-max-microvolt = <2800000>;
112			};
113
114			vtt_ddr: ldo3 {
115				regulator-name = "vtt_ddr";
116				regulator-always-on;
117				regulator-over-current-protection;
118				st,regulator-sink-source;
119			};
120
121			vdd_usb: ldo4 {
122				regulator-name = "vdd_usb";
123				regulator-min-microvolt = <3300000>;
124				regulator-max-microvolt = <3300000>;
125			};
126
127			vdd_sd: ldo5 {
128				regulator-name = "vdd_sd";
129				regulator-min-microvolt = <2900000>;
130				regulator-max-microvolt = <2900000>;
131				regulator-boot-on;
132			};
133
134			v1v8: ldo6 {
135				regulator-name = "v1v8";
136				regulator-min-microvolt = <1800000>;
137				regulator-max-microvolt = <1800000>;
138			};
139
140			vref_ddr: vref_ddr {
141				regulator-name = "vref_ddr";
142				regulator-always-on;
143			};
144
145			bst_out: boost {
146				regulator-name = "bst_out";
147			};
148
149			vbus_otg: pwr_sw1 {
150				regulator-name = "vbus_otg";
151			};
152
153			vbus_sw: pwr_sw2 {
154				regulator-name = "vbus_sw";
155				regulator-active-discharge = <1>;
156			};
157		};
158	};
159};
160
161&iwdg2 {
162	timeout-sec = <32>;
163	status = "okay";
164};
165
166&pwr_regulators {
167	vdd-supply = <&vdd>;
168	vdd_3v3_usbfs-supply = <&vdd_usb>;
169};
170
171&qspi {
172	pinctrl-names = "default";
173	pinctrl-0 = <&qspi_clk_pins_a
174		     &qspi_bk1_pins_a
175		     &qspi_cs1_pins_a>;
176	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
177	#address-cells = <1>;
178	#size-cells = <0>;
179	status = "okay";
180
181	flash0: flash@0 {
182		compatible = "jedec,spi-nor";
183		reg = <0>;
184		spi-rx-bus-width = <4>;
185		spi-max-frequency = <108000000>;
186		#address-cells = <1>;
187		#size-cells = <1>;
188	};
189};
190
191&rcc {
192	st,clksrc = <
193		CLK_MPU_PLL1P
194		CLK_AXI_PLL2P
195		CLK_MCU_PLL3P
196		CLK_RTC_LSE
197		CLK_MCO1_DISABLED
198		CLK_MCO2_PLL4
199		CLK_CKPER_HSE
200		CLK_FMC_ACLK
201		CLK_QSPI_ACLK
202		CLK_ETH_PLL4P
203		CLK_SDMMC12_PLL4P
204		CLK_DSI_DSIPLL
205		CLK_STGEN_HSE
206		CLK_USBPHY_HSE
207		CLK_SPI2S1_PLL3Q
208		CLK_SPI2S23_PLL3Q
209		CLK_SPI45_HSI
210		CLK_SPI6_HSI
211		CLK_I2C46_HSI
212		CLK_SDMMC3_PLL4P
213		CLK_USBO_USBPHY
214		CLK_ADC_CKPER
215		CLK_CEC_LSE
216		CLK_I2C12_HSI
217		CLK_I2C35_HSI
218		CLK_UART1_HSI
219		CLK_UART24_HSI
220		CLK_UART35_HSI
221		CLK_UART6_HSI
222		CLK_UART78_HSI
223		CLK_SPDIF_PLL4P
224		CLK_FDCAN_PLL4R
225		CLK_SAI1_PLL3Q
226		CLK_SAI2_PLL3Q
227		CLK_SAI3_PLL3Q
228		CLK_SAI4_PLL3Q
229		CLK_RNG1_CSI
230		CLK_RNG2_LSI
231		CLK_LPTIM1_PCLK1
232		CLK_LPTIM23_PCLK3
233		CLK_LPTIM45_LSE
234	>;
235
236	st,clkdiv = <
237		DIV(DIV_MPU, 1)
238		DIV(DIV_AXI, 0)
239		DIV(DIV_MCU, 0)
240		DIV(DIV_APB1, 1)
241		DIV(DIV_APB2, 1)
242		DIV(DIV_APB3, 1)
243		DIV(DIV_APB4, 1)
244		DIV(DIV_APB5, 2)
245		DIV(DIV_RTC, 23)
246		DIV(DIV_MCO1, 0)
247		DIV(DIV_MCO2, 1)
248	>;
249
250	st,pll_vco {
251		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
252			src = <CLK_PLL12_HSE>;
253			divmn = <2 65>;
254			frac = <0x1400>;
255		};
256
257		pll3_vco_417Mhz: pll3-vco-417Mhz {
258			src = <CLK_PLL3_HSE>;
259			divmn = <1 33>;
260			frac = <0x1a04>;
261		};
262
263		pll4_vco_600Mhz: pll4-vco-600hz {
264			src = <CLK_PLL4_HSE>;
265			divmn = <1 49>;
266		};
267	};
268
269	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
270	pll2: st,pll@1 {
271		compatible = "st,stm32mp1-pll";
272		reg = <1>;
273
274		st,pll = <&pll2_cfg1>;
275
276		pll2_cfg1: pll2_cfg1 {
277			st,pll_vco = <&pll2_vco_1066Mhz>;
278			st,pll_div_pqr = <1 0 0>;
279		};
280	};
281
282	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
283	pll3: st,pll@2 {
284		compatible = "st,stm32mp1-pll";
285		reg = <2>;
286
287		st,pll = <&pll3_cfg1>;
288
289		pll3_cfg1: pll3_cfg1 {
290			st,pll_vco = <&pll3_vco_417Mhz>;
291			st,pll_div_pqr = <1 16 36>;
292		};
293	};
294
295	/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
296	pll4: st,pll@3 {
297		compatible = "st,stm32mp1-pll";
298		reg = <3>;
299
300		st,pll = <&pll4_cfg1>;
301
302		pll4_cfg1: pll4_cfg1 {
303			st,pll_vco = <&pll4_vco_600Mhz>;
304			st,pll_div_pqr = <5 11 11>;
305		};
306	};
307};
308
309&rng1 {
310	status = "okay";
311};
312
313&rtc {
314	status = "okay";
315};
316
317&sdmmc1 {
318	pinctrl-names = "default";
319	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
320	disable-wp;
321	st,sig-dir;
322	st,neg-edge;
323	bus-width = <4>;
324	vmmc-supply = <&vdd_sd>;
325	status = "okay";
326};
327
328&sdmmc1_b4_pins_a {
329	/*
330	 * SD bus pull-up resistors:
331	 * - optional on SoMs with SD voltage translator
332	 * - mandatory on SoMs without SD voltage translator
333	 */
334	pins1 {
335		bias-pull-up;
336	};
337	pins2 {
338		bias-pull-up;
339	};
340};
341
342&sdmmc2 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
345	non-removable;
346	no-sd;
347	no-sdio;
348	st,neg-edge;
349	bus-width = <8>;
350	vmmc-supply = <&v3v3>;
351	vqmmc-supply = <&v3v3>;
352	mmc-ddr-3_3v;
353	status = "okay";
354};
355
356&uart4 {
357	pinctrl-names = "default";
358	pinctrl-0 = <&uart4_pins_a>;
359	status = "okay";
360};
361