1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp1-clksrc.h>
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		serial0 = &uart4;
13		serial1 = &usart3;
14		serial2 = &uart7;
15	};
16
17	memory@c0000000 {
18		device_type = "memory";
19		reg = <0xc0000000 0x20000000>;
20	};
21
22	vin: vin {
23		compatible = "regulator-fixed";
24		regulator-name = "vin";
25		regulator-min-microvolt = <5000000>;
26		regulator-max-microvolt = <5000000>;
27		regulator-always-on;
28	};
29};
30
31&bsec {
32	board_id: board-id@ec {
33		reg = <0xec 0x4>;
34		st,non-secure-otp;
35	};
36};
37
38&clk_hse {
39	st,digbypass;
40};
41
42&cpu0 {
43	cpu-supply = <&vddcore>;
44};
45
46&cpu1 {
47	cpu-supply = <&vddcore>;
48};
49
50&hash1 {
51	status = "okay";
52};
53
54&i2c4 {
55	pinctrl-names = "default";
56	pinctrl-0 = <&i2c4_pins_a>;
57	i2c-scl-rising-time-ns = <185>;
58	i2c-scl-falling-time-ns = <20>;
59	clock-frequency = <400000>;
60	status = "okay";
61
62	pmic: stpmic@33 {
63		compatible = "st,stpmic1";
64		reg = <0x33>;
65		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
66		interrupt-controller;
67		#interrupt-cells = <2>;
68		status = "okay";
69
70		regulators {
71			compatible = "st,stpmic1-regulators";
72			buck1-supply = <&vin>;
73			buck2-supply = <&vin>;
74			buck3-supply = <&vin>;
75			buck4-supply = <&vin>;
76			ldo1-supply = <&v3v3>;
77			ldo2-supply = <&vin>;
78			ldo3-supply = <&vdd_ddr>;
79			ldo4-supply = <&vin>;
80			ldo5-supply = <&vin>;
81			ldo6-supply = <&v3v3>;
82			vref_ddr-supply = <&vin>;
83			boost-supply = <&vin>;
84			pwr_sw1-supply = <&bst_out>;
85			pwr_sw2-supply = <&bst_out>;
86
87			vddcore: buck1 {
88				regulator-name = "vddcore";
89				regulator-min-microvolt = <1200000>;
90				regulator-max-microvolt = <1350000>;
91				regulator-always-on;
92				regulator-initial-mode = <0>;
93				regulator-over-current-protection;
94			};
95
96			vdd_ddr: buck2 {
97				regulator-name = "vdd_ddr";
98				regulator-min-microvolt = <1350000>;
99				regulator-max-microvolt = <1350000>;
100				regulator-always-on;
101				regulator-initial-mode = <0>;
102				regulator-over-current-protection;
103			};
104
105			vdd: buck3 {
106				regulator-name = "vdd";
107				regulator-min-microvolt = <3300000>;
108				regulator-max-microvolt = <3300000>;
109				regulator-always-on;
110				st,mask-reset;
111				regulator-initial-mode = <0>;
112				regulator-over-current-protection;
113			};
114
115			v3v3: buck4 {
116				regulator-name = "v3v3";
117				regulator-min-microvolt = <3300000>;
118				regulator-max-microvolt = <3300000>;
119				regulator-always-on;
120				regulator-over-current-protection;
121				regulator-initial-mode = <0>;
122			};
123
124			v1v8_audio: ldo1 {
125				regulator-name = "v1v8_audio";
126				regulator-min-microvolt = <1800000>;
127				regulator-max-microvolt = <1800000>;
128				regulator-always-on;
129			};
130
131			v3v3_hdmi: ldo2 {
132				regulator-name = "v3v3_hdmi";
133				regulator-min-microvolt = <3300000>;
134				regulator-max-microvolt = <3300000>;
135				regulator-always-on;
136			};
137
138			vtt_ddr: ldo3 {
139				regulator-name = "vtt_ddr";
140				regulator-always-on;
141				regulator-over-current-protection;
142				st,regulator-sink-source;
143			};
144
145			vdd_usb: ldo4 {
146				regulator-name = "vdd_usb";
147				regulator-min-microvolt = <3300000>;
148				regulator-max-microvolt = <3300000>;
149			};
150
151			vdda: ldo5 {
152				regulator-name = "vdda";
153				regulator-min-microvolt = <2900000>;
154				regulator-max-microvolt = <2900000>;
155				regulator-boot-on;
156			};
157
158			v1v2_hdmi: ldo6 {
159				regulator-name = "v1v2_hdmi";
160				regulator-min-microvolt = <1200000>;
161				regulator-max-microvolt = <1200000>;
162				regulator-always-on;
163			};
164
165			vref_ddr: vref_ddr {
166				regulator-name = "vref_ddr";
167				regulator-always-on;
168			};
169
170			bst_out: boost {
171				regulator-name = "bst_out";
172			};
173
174			vbus_otg: pwr_sw1 {
175				regulator-name = "vbus_otg";
176			};
177
178			vbus_sw: pwr_sw2 {
179				regulator-name = "vbus_sw";
180				regulator-active-discharge = <1>;
181			};
182		};
183	};
184};
185
186&iwdg2 {
187	timeout-sec = <32>;
188	status = "okay";
189};
190
191&pwr_regulators {
192	vdd-supply = <&vdd>;
193	vdd_3v3_usbfs-supply = <&vdd_usb>;
194};
195
196&rcc {
197	st,clksrc = <
198		CLK_MPU_PLL1P
199		CLK_AXI_PLL2P
200		CLK_MCU_PLL3P
201		CLK_MCO1_DISABLED
202		CLK_MCO2_DISABLED
203		CLK_CKPER_HSE
204		CLK_FMC_ACLK
205		CLK_QSPI_ACLK
206		CLK_ETH_PLL4P
207		CLK_SDMMC12_PLL4P
208		CLK_DSI_DSIPLL
209		CLK_STGEN_HSE
210		CLK_USBPHY_HSE
211		CLK_SPI2S1_PLL3Q
212		CLK_SPI2S23_PLL3Q
213		CLK_SPI45_HSI
214		CLK_SPI6_HSI
215		CLK_I2C46_HSI
216		CLK_SDMMC3_PLL4P
217		CLK_USBO_USBPHY
218		CLK_ADC_CKPER
219		CLK_CEC_LSE
220		CLK_I2C12_HSI
221		CLK_I2C35_HSI
222		CLK_UART1_HSI
223		CLK_UART24_HSI
224		CLK_UART35_HSI
225		CLK_UART6_HSI
226		CLK_UART78_HSI
227		CLK_SPDIF_PLL4P
228		CLK_FDCAN_PLL4R
229		CLK_SAI1_PLL3Q
230		CLK_SAI2_PLL3Q
231		CLK_SAI3_PLL3Q
232		CLK_SAI4_PLL3Q
233		CLK_RNG1_CSI
234		CLK_RNG2_LSI
235		CLK_LPTIM1_PCLK1
236		CLK_LPTIM23_PCLK3
237		CLK_LPTIM45_LSE
238	>;
239
240	st,clkdiv = <
241		DIV(DIV_MPU, 1)
242		DIV(DIV_AXI, 0)
243		DIV(DIV_MCU, 0)
244		DIV(DIV_APB1, 1)
245		DIV(DIV_APB2, 1)
246		DIV(DIV_APB3, 1)
247		DIV(DIV_APB4, 1)
248		DIV(DIV_APB5, 2)
249		DIV(DIV_MCO1, 0)
250		DIV(DIV_MCO2, 0)
251	>;
252
253	st,pll_vco {
254		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
255			src = <CLK_PLL12_HSE>;
256			divmn = <2 65>;
257			frac = <0x1400>;
258		};
259
260		pll3_vco_417Mhz: pll3-vco-417Mhz {
261			src = <CLK_PLL3_HSE>;
262			divmn = <1 33>;
263			frac = <0x1a04>;
264		};
265
266		pll4_vco_594Mhz: pll4-vco-594Mhz {
267			src = <CLK_PLL4_HSE>;
268			divmn = <3 98>;
269		};
270	};
271
272	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
273	pll2: st,pll@1 {
274		compatible = "st,stm32mp1-pll";
275		reg = <1>;
276
277		st,pll = <&pll2_cfg1>;
278
279		pll2_cfg1: pll2_cfg1 {
280			st,pll_vco = <&pll2_vco_1066Mhz>;
281			st,pll_div_pqr = <1 0 0>;
282		};
283	};
284
285	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
286	pll3: st,pll@2 {
287		compatible = "st,stm32mp1-pll";
288		reg = <2>;
289
290		st,pll = <&pll3_cfg1>;
291
292		pll3_cfg1: pll3_cfg1 {
293			st,pll_vco = <&pll3_vco_417Mhz>;
294			st,pll_div_pqr = <1 16 36>;
295		};
296	};
297
298	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
299	pll4: st,pll@3 {
300		compatible = "st,stm32mp1-pll";
301		reg = <3>;
302
303		st,pll = <&pll4_cfg1>;
304
305		pll4_cfg1: pll4_cfg1 {
306			st,pll_vco = <&pll4_vco_594Mhz>;
307			st,pll_div_pqr = <5 7 7>;
308		};
309	};
310};
311
312&rng1 {
313	status = "okay";
314};
315
316&rtc {
317	status = "okay";
318};
319
320&sdmmc1 {
321	pinctrl-names = "default";
322	pinctrl-0 = <&sdmmc1_b4_pins_a>;
323	disable-wp;
324	st,neg-edge;
325	bus-width = <4>;
326	vmmc-supply = <&v3v3>;
327	status = "okay";
328};
329
330&uart4 {
331	pinctrl-names = "default";
332	pinctrl-0 = <&uart4_pins_a>;
333	status = "okay";
334};
335
336&uart7 {
337	pinctrl-names = "default";
338	pinctrl-0 = <&uart7_pins_c>;
339	status = "disabled";
340};
341
342&usart3 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&usart3_pins_c>;
345	uart-has-rtscts;
346	status = "disabled";
347};
348
349&usbotg_hs {
350	phys = <&usbphyc_port1 0>;
351	phy-names = "usb2-phy";
352	usb-role-switch;
353	status = "okay";
354};
355
356&usbphyc {
357	status = "okay";
358};
359
360&usbphyc_port0 {
361	phy-supply = <&vdd_usb>;
362};
363
364&usbphyc_port1 {
365	phy-supply = <&vdd_usb>;
366};
367