1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp25-clks.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/reset/stm32mp25-resets.h>
10
11/ {
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-a35";
21			device_type = "cpu";
22			reg = <0>;
23			enable-method = "psci";
24		};
25	};
26
27	clocks {
28		clk_hse: clk-hse {
29			#clock-cells = <0>;
30			compatible = "fixed-clock";
31			clock-frequency = <48000000>;
32		};
33
34		clk_hsi: clk-hsi {
35			#clock-cells = <0>;
36			compatible = "fixed-clock";
37			clock-frequency = <64000000>;
38		};
39
40		clk_lse: clk-lse {
41			#clock-cells = <0>;
42			compatible = "fixed-clock";
43			clock-frequency = <32768>;
44		};
45
46		clk_lsi: clk-lsi {
47			#clock-cells = <0>;
48			compatible = "fixed-clock";
49			clock-frequency = <32000>;
50		};
51
52		clk_msi: clk-msi {
53			#clock-cells = <0>;
54			compatible = "fixed-clock";
55			clock-frequency = <16000000>;
56		};
57	};
58
59	intc: interrupt-controller@4ac00000 {
60		compatible = "arm,cortex-a7-gic";
61		#interrupt-cells = <3>;
62		#address-cells = <1>;
63		interrupt-controller;
64		reg = <0x0 0x4ac10000 0x0 0x1000>,
65		      <0x0 0x4ac20000 0x0 0x2000>,
66		      <0x0 0x4ac40000 0x0 0x2000>,
67		      <0x0 0x4ac60000 0x0 0x2000>;
68	};
69
70	timer {
71		compatible = "arm,armv8-timer";
72		interrupt-parent = <&intc>;
73		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77		always-on;
78	};
79
80	soc@0 {
81		compatible = "simple-bus";
82		#address-cells = <1>;
83		#size-cells = <1>;
84		interrupt-parent = <&intc>;
85		ranges = <0x0 0x0 0x0 0x80000000>;
86
87		rifsc: rifsc@42080000 {
88			compatible = "st,stm32mp25-rifsc";
89			reg = <0x42080000 0x1000>;
90			#address-cells = <1>;
91			#size-cells = <1>;
92
93			usart2: serial@400e0000 {
94				compatible = "st,stm32h7-uart";
95				reg = <0x400e0000 0x400>;
96				clocks = <&rcc CK_KER_USART2>;
97				resets = <&rcc USART2_R>;
98				status = "disabled";
99			};
100
101			usart3: serial@400f0000 {
102				compatible = "st,stm32h7-uart";
103				reg = <0x400f0000 0x400>;
104				clocks = <&rcc CK_KER_USART3>;
105				resets = <&rcc USART3_R>;
106				status = "disabled";
107			};
108
109			uart4: serial@40100000 {
110				compatible = "st,stm32h7-uart";
111				reg = <0x40100000 0x400>;
112				clocks = <&rcc CK_KER_UART4>;
113				resets = <&rcc UART4_R>;
114				status = "disabled";
115			};
116
117			uart5: serial@40110000 {
118				compatible = "st,stm32h7-uart";
119				reg = <0x40110000 0x400>;
120				clocks = <&rcc CK_KER_UART5>;
121				resets = <&rcc UART5_R>;
122				status = "disabled";
123			};
124
125			i2c1: i2c@40120000 {
126				compatible = "st,stm32mp25-i2c";
127				reg = <0x40120000 0x400>;
128				clocks = <&rcc CK_KER_I2C1>;
129				resets = <&rcc I2C1_R>;
130				status = "disabled";
131			};
132
133			i2c2: i2c@40130000 {
134				compatible = "st,stm32mp25-i2c";
135				reg = <0x40130000 0x400>;
136				clocks = <&rcc CK_KER_I2C2>;
137				resets = <&rcc I2C2_R>;
138				status = "disabled";
139			};
140
141			i2c3: i2c@40140000 {
142				compatible = "st,stm32mp25-i2c";
143				reg = <0x40140000 0x400>;
144				clocks = <&rcc CK_KER_I2C3>;
145				resets = <&rcc I2C3_R>;
146				status = "disabled";
147			};
148
149			i2c4: i2c@40150000 {
150				compatible = "st,stm32mp25-i2c";
151				reg = <0x40150000 0x400>;
152				clocks = <&rcc CK_KER_I2C4>;
153				resets = <&rcc I2C4_R>;
154				status = "disabled";
155			};
156
157			i2c5: i2c@40160000 {
158				compatible = "st,stm32mp25-i2c";
159				reg = <0x40160000 0x400>;
160				clocks = <&rcc CK_KER_I2C5>;
161				resets = <&rcc I2C5_R>;
162				status = "disabled";
163			};
164
165			i2c6: i2c@40170000 {
166				compatible = "st,stm32mp25-i2c";
167				reg = <0x40170000 0x400>;
168				clocks = <&rcc CK_KER_I2C6>;
169				resets = <&rcc I2C6_R>;
170				status = "disabled";
171			};
172
173			i2c7: i2c@40180000 {
174				compatible = "st,stm32mp25-i2c";
175				reg = <0x40180000 0x400>;
176				clocks = <&rcc CK_KER_I2C7>;
177				resets = <&rcc I2C7_R>;
178				status = "disabled";
179			};
180
181			usart6: serial@40220000 {
182				compatible = "st,stm32h7-uart";
183				reg = <0x40220000 0x400>;
184				clocks = <&rcc CK_KER_USART6>;
185				resets = <&rcc USART6_R>;
186				status = "disabled";
187			};
188
189			uart9: serial@402c0000 {
190				compatible = "st,stm32h7-uart";
191				reg = <0x402c0000 0x400>;
192				clocks = <&rcc CK_KER_UART9>;
193				resets = <&rcc UART9_R>;
194				status = "disabled";
195			};
196
197			usart1: serial@40330000 {
198				compatible = "st,stm32h7-uart";
199				reg = <0x40330000 0x400>;
200				clocks = <&rcc CK_KER_USART1>;
201				resets = <&rcc USART1_R>;
202				status = "disabled";
203			};
204
205			uart7: serial@40370000 {
206				compatible = "st,stm32h7-uart";
207				reg = <0x40370000 0x400>;
208				clocks = <&rcc CK_KER_UART7>;
209				resets = <&rcc UART7_R>;
210				status = "disabled";
211			};
212
213			uart8: serial@40380000 {
214				compatible = "st,stm32h7-uart";
215				reg = <0x40380000 0x400>;
216				clocks = <&rcc CK_KER_UART8>;
217				resets = <&rcc UART8_R>;
218				status = "disabled";
219			};
220
221			i2c8: i2c@46040000 {
222				compatible = "st,stm32mp25-i2c";
223				reg = <0x46040000 0x400>;
224				clocks = <&rcc CK_KER_I2C8>;
225				resets = <&rcc I2C8_R>;
226				status = "disabled";
227			};
228
229			sdmmc1: mmc@48220000 {
230				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
231				arm,primecell-periphid = <0x00353180>;
232				reg = <0x48220000 0x400>, <0x44230400 0x8>;
233				clocks = <&rcc CK_KER_SDMMC1>;
234				clock-names = "apb_pclk";
235				resets = <&rcc SDMMC1_R>;
236				cap-sd-highspeed;
237				cap-mmc-highspeed;
238				max-frequency = <120000000>;
239				status = "disabled";
240			};
241
242			sdmmc2: mmc@48230000 {
243				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
244				arm,primecell-periphid = <0x00353180>;
245				reg = <0x48230000 0x400>, <0x44230800 0x8>;
246				clocks = <&rcc CK_KER_SDMMC2>;
247				clock-names = "apb_pclk";
248				resets = <&rcc SDMMC2_R>;
249				cap-sd-highspeed;
250				cap-mmc-highspeed;
251				max-frequency = <120000000>;
252				status = "disabled";
253			};
254		};
255
256		bsec: efuse@44000000 {
257			compatible = "st,stm32mp25-bsec";
258			reg = <0x44000000 0x400>;
259			#address-cells = <1>;
260			#size-cells = <1>;
261
262			uid_otp: uid-otp@14 {
263				reg = <0x14 0xc>;
264			};
265			part_number_otp: part-number-otp@24 {
266				reg = <0x24 0x4>;
267			};
268			nand_otp: otp16@40 {
269				reg = <0x40 0x4>;
270			};
271			lifecycle2_otp: otp18@48 {
272				reg = <0x48 0x4>;
273			};
274			nand2_otp: otp20@50 {
275				reg = <0x50 0x4>;
276			};
277			rev_otp@198 {
278				reg = <0x198 0x4>;
279			};
280			package_otp: package-otp@1e8 {
281				reg = <0x1e8 0x1>;
282			};
283			hconf1_otp: otp124@1f0 {
284				reg = <0x1f0 0x4>;
285			};
286			pkh_otp: otp144@240 {
287				reg = <0x240 0x20>;
288			};
289			oem_fip_enc_key: otp260@410 {
290				reg = <0x410 0x20>;
291			};
292		};
293
294		rcc: rcc@44200000 {
295			compatible = "st,stm32mp25-rcc";
296			reg = <0x44200000 0x10000>;
297			#clock-cells = <1>;
298			#reset-cells = <1>;
299		};
300
301		pwr: pwr@44210000 {
302			compatible = "st,stm32mp25-pwr";
303			reg = <0x44210000 0x400>;
304
305			vddio1: vddio1 {
306				regulator-name = "vddio1";
307			};
308
309			vddio2: vddio2 {
310				regulator-name = "vddio2";
311			};
312
313			vddio3: vddio3 {
314				regulator-name = "vddio3";
315			};
316
317			vddio4: vddio4 {
318				regulator-name = "vddio4";
319			};
320
321			vddio: vddio {
322				regulator-name = "vddio";
323			};
324		};
325
326		syscfg: syscon@44230000 {
327			compatible = "st,stm32mp25-syscfg", "syscon";
328			reg = <0x44230000 0x10000>;
329		};
330
331		ddr: ddr@48040000 {
332			compatible = "st,stm32mp2-ddr";
333			reg = <0x48040000 0x10000>,
334			      <0x48c00000 0x400000>;
335			status = "okay";
336		};
337
338		pinctrl: pinctrl@44240000 {
339			#address-cells = <1>;
340			#size-cells = <1>;
341			compatible = "st,stm32mp257-pinctrl";
342			ranges = <0 0x44240000 0xa0400>;
343
344			gpioa: gpio@44240000 {
345				gpio-controller;
346				#gpio-cells = <2>;
347				interrupt-controller;
348				#interrupt-cells = <2>;
349				reg = <0x0 0x400>;
350				clocks = <&rcc CK_BUS_GPIOA>;
351				st,bank-name = "GPIOA";
352				status = "disabled";
353			};
354
355			gpiob: gpio@44250000 {
356				gpio-controller;
357				#gpio-cells = <2>;
358				interrupt-controller;
359				#interrupt-cells = <2>;
360				reg = <0x10000 0x400>;
361				clocks = <&rcc CK_BUS_GPIOB>;
362				st,bank-name = "GPIOB";
363				status = "disabled";
364			};
365
366			gpioc: gpio@44260000 {
367				gpio-controller;
368				#gpio-cells = <2>;
369				interrupt-controller;
370				#interrupt-cells = <2>;
371				reg = <0x20000 0x400>;
372				clocks = <&rcc CK_BUS_GPIOC>;
373				st,bank-name = "GPIOC";
374				status = "disabled";
375			};
376
377			gpiod: gpio@44270000 {
378				gpio-controller;
379				#gpio-cells = <2>;
380				interrupt-controller;
381				#interrupt-cells = <2>;
382				reg = <0x30000 0x400>;
383				clocks = <&rcc CK_BUS_GPIOD>;
384				st,bank-name = "GPIOD";
385				status = "disabled";
386			};
387
388			gpioe: gpio@44280000 {
389				gpio-controller;
390				#gpio-cells = <2>;
391				interrupt-controller;
392				#interrupt-cells = <2>;
393				reg = <0x40000 0x400>;
394				clocks = <&rcc CK_BUS_GPIOE>;
395				st,bank-name = "GPIOE";
396				status = "disabled";
397			};
398
399			gpiof: gpio@44290000 {
400				gpio-controller;
401				#gpio-cells = <2>;
402				interrupt-controller;
403				#interrupt-cells = <2>;
404				reg = <0x50000 0x400>;
405				clocks = <&rcc CK_BUS_GPIOF>;
406				st,bank-name = "GPIOF";
407				status = "disabled";
408			};
409
410			gpiog: gpio@442a0000 {
411				gpio-controller;
412				#gpio-cells = <2>;
413				interrupt-controller;
414				#interrupt-cells = <2>;
415				reg = <0x60000 0x400>;
416				clocks = <&rcc CK_BUS_GPIOG>;
417				st,bank-name = "GPIOG";
418				status = "disabled";
419			};
420
421			gpioh: gpio@442b0000 {
422				gpio-controller;
423				#gpio-cells = <2>;
424				interrupt-controller;
425				#interrupt-cells = <2>;
426				reg = <0x70000 0x400>;
427				clocks = <&rcc CK_BUS_GPIOH>;
428				st,bank-name = "GPIOH";
429				status = "disabled";
430			};
431
432			gpioi: gpio@442c0000 {
433				gpio-controller;
434				#gpio-cells = <2>;
435				interrupt-controller;
436				#interrupt-cells = <2>;
437				reg = <0x80000 0x400>;
438				clocks = <&rcc CK_BUS_GPIOI>;
439				st,bank-name = "GPIOI";
440				status = "disabled";
441			};
442
443			gpioj: gpio@442d0000 {
444				gpio-controller;
445				#gpio-cells = <2>;
446				interrupt-controller;
447				#interrupt-cells = <2>;
448				reg = <0x90000 0x400>;
449				clocks = <&rcc CK_BUS_GPIOJ>;
450				st,bank-name = "GPIOJ";
451				status = "disabled";
452			};
453
454			gpiok: gpio@442e0000 {
455				gpio-controller;
456				#gpio-cells = <2>;
457				interrupt-controller;
458				#interrupt-cells = <2>;
459				reg = <0xa0000 0x400>;
460				clocks = <&rcc CK_BUS_GPIOK>;
461				st,bank-name = "GPIOK";
462				status = "disabled";
463			};
464		};
465
466		pinctrl_z: pinctrl@46200000 {
467			#address-cells = <1>;
468			#size-cells = <1>;
469			compatible = "st,stm32mp257-z-pinctrl";
470			ranges = <0 0x46200000 0x400>;
471
472			gpioz: gpio@46200000 {
473				gpio-controller;
474				#gpio-cells = <2>;
475				interrupt-controller;
476				#interrupt-cells = <2>;
477				reg = <0 0x400>;
478				clocks = <&rcc CK_BUS_GPIOZ>;
479				st,bank-name = "GPIOZ";
480				st,bank-ioport = <11>;
481				status = "disabled";
482			};
483
484		};
485	};
486};
487