1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 /* 51 * Add some dummy entropy for Linux so it 52 * doesn't delay the boot waiting for it. 53 */ 54 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 55 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 core4 { 83 cpu = <&CPU4>; 84 }; 85 core5 { 86 cpu = <&CPU5>; 87 }; 88 core6 { 89 cpu = <&CPU6>; 90 }; 91 core7 { 92 cpu = <&CPU7>; 93 }; 94 }; 95 }; 96 97 /* 98 * The timings below are just to demonstrate working cpuidle. 99 * These values may be inaccurate. 100 */ 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 arm,psci-suspend-param = <0x0010000>; 107 local-timer-stop; 108 entry-latency-us = <300>; 109 exit-latency-us = <1200>; 110 min-residency-us = <2000>; 111 }; 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 arm,psci-suspend-param = <0x1010000>; 115 local-timer-stop; 116 entry-latency-us = <400>; 117 exit-latency-us = <1200>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 amus { 123 amu: amu-0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 mpmm_gear0: counter@0 { 128 reg = <0>; 129 enable-at-el3; 130 }; 131 132 mpmm_gear1: counter@1 { 133 reg = <1>; 134 enable-at-el3; 135 }; 136 137 mpmm_gear2: counter@2 { 138 reg = <2>; 139 enable-at-el3; 140 }; 141 }; 142 }; 143 144 CPU0:cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0>; 148 enable-method = "psci"; 149 clocks = <&scmi_dvfs 0>; 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 151 capacity-dmips-mhz = <LIT_CAPACITY>; 152 amu = <&amu>; 153 supports-mpmm; 154 }; 155 156 CPU1:cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x100>; 160 enable-method = "psci"; 161 clocks = <&scmi_dvfs 0>; 162 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 163 capacity-dmips-mhz = <LIT_CAPACITY>; 164 amu = <&amu>; 165 supports-mpmm; 166 }; 167 168 CPU2:cpu@200 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x200>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 amu = <&amu>; 175 supports-mpmm; 176 }; 177 178 CPU3:cpu@300 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x300>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 amu = <&amu>; 185 supports-mpmm; 186 }; 187 188 CPU4:cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,armv8"; 191 reg = <0x400>; 192 enable-method = "psci"; 193 clocks = <&scmi_dvfs 1>; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 capacity-dmips-mhz = <MID_CAPACITY>; 196 amu = <&amu>; 197 supports-mpmm; 198 }; 199 200 CPU5:cpu@500 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x500>; 204 enable-method = "psci"; 205 clocks = <&scmi_dvfs 1>; 206 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 207 capacity-dmips-mhz = <MID_CAPACITY>; 208 amu = <&amu>; 209 supports-mpmm; 210 }; 211 212 CPU6:cpu@600 { 213 device_type = "cpu"; 214 compatible = "arm,armv8"; 215 reg = <0x600>; 216 enable-method = "psci"; 217 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 218 amu = <&amu>; 219 supports-mpmm; 220 }; 221 222 CPU7:cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,armv8"; 225 reg = <0x700>; 226 enable-method = "psci"; 227 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 228 amu = <&amu>; 229 supports-mpmm; 230 }; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 linux,cma { 239 compatible = "shared-dma-pool"; 240 reusable; 241 size = <0x0 0x8000000>; 242 linux,cma-default; 243 }; 244 245 optee { 246 compatible = "restricted-dma-pool"; 247 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 248 }; 249 250 }; 251 252 memory { 253 device_type = "memory"; 254 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 255 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 256 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 257 }; 258 259 psci { 260 compatible = "arm,psci-1.0", "arm,psci-0.2"; 261 method = "smc"; 262 }; 263 264 cpu-pmu-little { 265 compatible = LIT_CPU_PMU_COMPATIBLE; 266 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 267 status = "okay"; 268 }; 269 270 cpu-pmu-mid { 271 compatible = MID_CPU_PMU_COMPATIBLE; 272 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 273 status = "okay"; 274 }; 275 276 cpu-pmu-big { 277 compatible = BIG_CPU_PMU_COMPATIBLE; 278 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 279 status = "okay"; 280 }; 281 282 sram: sram@6000000 { 283 compatible = "mmio-sram"; 284 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 285 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 289 290 cpu_scp_scmi_a2p: scp-shmem@0 { 291 compatible = "arm,scmi-shmem"; 292 reg = <0x0 0x80>; 293 }; 294 }; 295 296 mbox_db_rx: mhu@MHU_RX_ADDR { 297 compatible = MHU_RX_COMPAT; 298 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 299 clocks = <&soc_refclk>; 300 clock-names = "apb_pclk"; 301 #mbox-cells = <MHU_MBOX_CELLS>; 302 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 303 interrupt-names = MHU_RX_INT_NAME; 304 }; 305 306 mbox_db_tx: mhu@MHU_TX_ADDR { 307 compatible = MHU_TX_COMPAT; 308 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 309 clocks = <&soc_refclk>; 310 clock-names = "apb_pclk"; 311 #mbox-cells = <MHU_MBOX_CELLS>; 312 interrupt-names = MHU_TX_INT_NAME; 313 }; 314 315 firmware { 316 scmi { 317 compatible = "arm,scmi"; 318 mbox-names = "tx", "rx"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322#if TC_SCMI_PD_CTRL_EN 323 scmi_devpd: protocol@11 { 324 reg = <0x11>; 325 #power-domain-cells = <1>; 326 }; 327#endif /* TC_SCMI_PD_CTRL_EN */ 328 329 scmi_dvfs: protocol@13 { 330 reg = <0x13>; 331 #clock-cells = <1>; 332 }; 333 334 scmi_clk: protocol@14 { 335 reg = <0x14>; 336 #clock-cells = <1>; 337 }; 338 }; 339 }; 340 341 gic: interrupt-controller@GIC_CTRL_ADDR { 342 compatible = "arm,gic-v3"; 343 #address-cells = <2>; 344 #interrupt-cells = <4>; 345 #size-cells = <2>; 346 ranges; 347 interrupt-controller; 348 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 349 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 350 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 351 }; 352 353 timer { 354 compatible = "arm,armv8-timer"; 355 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 356 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 357 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 358 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 359 }; 360 361 spe-pmu-mid { 362 compatible = "arm,statistical-profiling-extension-v1"; 363 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 364 status = "disabled"; 365 }; 366 367 spe-pmu-big { 368 compatible = "arm,statistical-profiling-extension-v1"; 369 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 370 status = "disabled"; 371 }; 372 373 soc_refclk: refclk { 374 compatible = "fixed-clock"; 375 #clock-cells = <0>; 376 clock-frequency = <1000000000>; 377 clock-output-names = "apb_pclk"; 378 }; 379 380 soc_refclk60mhz: refclk60mhz { 381 compatible = "fixed-clock"; 382 #clock-cells = <0>; 383 clock-frequency = <60000000>; 384 clock-output-names = "iofpga_clk"; 385 }; 386 387 soc_uartclk: uartclk { 388 compatible = "fixed-clock"; 389 #clock-cells = <0>; 390 clock-frequency = <UARTCLK_FREQ>; 391 clock-output-names = "uartclk"; 392 }; 393 394 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 395 os_uart: serial@2a400000 { 396 compatible = "arm,pl011", "arm,primecell"; 397 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 398 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 399 clocks = <&soc_uartclk>, <&soc_refclk>; 400 clock-names = "uartclk", "apb_pclk"; 401 status = "okay"; 402 }; 403 404#if !TC_DPU_USE_SCMI_CLK 405 dpu_aclk: dpu_aclk { 406 compatible = "fixed-clock"; 407 #clock-cells = <0>; 408 clock-frequency = <VENCODER_TIMING_CLK>; 409 clock-output-names = "fpga:dpu_aclk"; 410 }; 411 412 dpu_pixel_clk: dpu-pixel-clk { 413 compatible = "fixed-clock"; 414 #clock-cells = <0>; 415 clock-frequency = <VENCODER_TIMING_CLK>; 416 clock-output-names = "pxclk"; 417 }; 418#endif /* !TC_DPU_USE_SCMI_CLK */ 419 420 vencoder { 421 compatible = "drm,virtual-encoder"; 422 port { 423 vencoder_in: endpoint { 424 remote-endpoint = <&dp_pl0_out0>; 425 }; 426 }; 427 428 display-timings { 429 timing-panel { 430 VENCODER_TIMING; 431 }; 432 }; 433 434 }; 435 436 ethernet: ethernet@ETHERNET_ADDR { 437 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 438 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 439 440 reg-io-width = <2>; 441 smsc,irq-push-pull; 442 }; 443 444 bp_clock24mhz: clock24mhz { 445 compatible = "fixed-clock"; 446 #clock-cells = <0>; 447 clock-frequency = <24000000>; 448 clock-output-names = "bp:clock24mhz"; 449 }; 450 451 sysreg: sysreg@SYS_REGS_ADDR { 452 compatible = "arm,vexpress-sysreg"; 453 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 }; 457 458 fixed_3v3: v2m-3v3 { 459 compatible = "regulator-fixed"; 460 regulator-name = "3V3"; 461 regulator-min-microvolt = <3300000>; 462 regulator-max-microvolt = <3300000>; 463 regulator-always-on; 464 }; 465 466 mmci: mmci@MMC_ADDR { 467 compatible = "arm,pl180", "arm,primecell"; 468 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 469 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 470 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 471 wp-gpios = <&sysreg 1 0>; 472 bus-width = <4>; 473 max-frequency = <25000000>; 474 vmmc-supply = <&fixed_3v3>; 475 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 476 clock-names = "mclk", "apb_pclk"; 477 }; 478 479 gpu_clk: gpu_clk { 480 compatible = "fixed-clock"; 481 #clock-cells = <0>; 482 clock-frequency = <1000000000>; 483 }; 484 485 gpu_core_clk: gpu_core_clk { 486 compatible = "fixed-clock"; 487 #clock-cells = <0>; 488 clock-frequency = <1000000000>; 489 }; 490 491 gpu: gpu@2d000000 { 492 compatible = "arm,mali-midgard"; 493 reg = <0x0 0x2d000000 0x0 0x200000>; 494 clocks = <&gpu_core_clk>; 495 clock-names = "shadercores"; 496#if TC_SCMI_PD_CTRL_EN 497 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 498 scmi-perf-domain = <3>; 499#endif /* TC_SCMI_PD_CTRL_EN */ 500 501 pbha { 502 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 503 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 504 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 505 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 506 <22 0x32>, <24 0x22>, <28 0x32>; 507 propagate-bits = <0x0f>; 508 }; 509 }; 510 511 power_model_simple { 512 /* 513 * Numbers used are irrelevant to Titan, 514 * it helps suppressing the kernel warnings. 515 */ 516 compatible = "arm,mali-simple-power-model"; 517 static-coefficient = <2427750>; 518 dynamic-coefficient = <4687>; 519 ts = <20000 2000 (-20) 2>; 520 thermal-zone = ""; 521 }; 522 523 smmu_600: smmu@2ce00000 { 524 compatible = "arm,smmu-v3"; 525 reg = <0 0x2ce00000 0 0x20000>; 526 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 527 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 528 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 529 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 530 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 531 #iommu-cells = <1>; 532 status = "disabled"; 533 }; 534 535 smmu_700: iommu@3f000000 { 536 #iommu-cells = <1>; 537 compatible = "arm,smmu-v3"; 538 reg = <0x0 0x3f000000 0x0 0x5000000>; 539 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 540 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 541 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 542 interrupt-names = "eventq", "cmdq-sync", "gerror"; 543 dma-coherent; 544 status = "disabled"; 545 }; 546 547 smmu_700_dpu: iommu@4002a00000 { 548 #iommu-cells = <1>; 549 compatible = "arm,smmu-v3"; 550 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 551 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 552 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 553 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 554 interrupt-names = "eventq", "cmdq-sync", "gerror"; 555 dma-coherent; 556 status = "disabled"; 557 }; 558 559 dp0: display@DPU_ADDR { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 compatible = "arm,mali-d71"; 563 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 564 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 565 interrupt-names = "DPU"; 566 DPU_CLK_ATTR1; 567 568 pl0: pipeline@0 { 569 reg = <0>; 570 DPU_CLK_ATTR2; 571 pl_id = <0>; 572 ports { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 port@0 { 576 reg = <0>; 577 dp_pl0_out0: endpoint { 578 remote-endpoint = <&vencoder_in>; 579 }; 580 }; 581 }; 582 }; 583 584 pl1: pipeline@1 { 585 reg = <1>; 586 DPU_CLK_ATTR3; 587 pl_id = <1>; 588 ports { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 port@0 { 592 reg = <0>; 593 }; 594 }; 595 }; 596 }; 597 598 /* 599 * L3 cache in the DSU is the Memory System Component (MSC) 600 * The MPAM registers are accessed through utility bus in the DSU 601 */ 602 msc0 { 603 compatible = "arm,mpam-msc"; 604 reg = <MPAM_ADDR 0x0 0x2000>; 605 }; 606 607 ete0 { 608 compatible = "arm,embedded-trace-extension"; 609 cpu = <&CPU0>; 610 }; 611 612 ete1 { 613 compatible = "arm,embedded-trace-extension"; 614 cpu = <&CPU1>; 615 }; 616 617 ete2 { 618 compatible = "arm,embedded-trace-extension"; 619 cpu = <&CPU2>; 620 }; 621 622 ete3 { 623 compatible = "arm,embedded-trace-extension"; 624 cpu = <&CPU3>; 625 }; 626 627 ete4 { 628 compatible = "arm,embedded-trace-extension"; 629 cpu = <&CPU4>; 630 }; 631 632 ete5 { 633 compatible = "arm,embedded-trace-extension"; 634 cpu = <&CPU5>; 635 }; 636 637 ete6 { 638 compatible = "arm,embedded-trace-extension"; 639 cpu = <&CPU6>; 640 }; 641 642 ete7 { 643 compatible = "arm,embedded-trace-extension"; 644 cpu = <&CPU7>; 645 }; 646 647 trbe { 648 compatible = "arm,trace-buffer-extension"; 649 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 650 }; 651 652 trusty { 653 #size-cells = <0x02>; 654 #address-cells = <0x02>; 655 ranges = <0x00>; 656 compatible = "android,trusty-v1"; 657 658 virtio { 659 compatible = "android,trusty-virtio-v1"; 660 }; 661 662 test { 663 compatible = "android,trusty-test-v1"; 664 }; 665 666 log { 667 compatible = "android,trusty-log-v1"; 668 }; 669 670 irq { 671 ipi-range = <0x08 0x0f 0x08>; 672 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 673 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 674 compatible = "android,trusty-irq-v1"; 675 }; 676 }; 677 678 /* used in U-boot, Linux doesn't care */ 679 arm_ffa { 680 compatible = "arm,ffa"; 681 method = "smc"; 682 }; 683}; 684