1/*
2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <platform_def.h>
11
12#if TARGET_FLAVOUR_FVP
13#define LIT_CAPACITY			406
14#define MID_CAPACITY			912
15#else /* TARGET_FLAVOUR_FPGA */
16#define LIT_CAPACITY			280
17#define MID_CAPACITY			775
18/* this is an area optimized configuration of the big core */
19#define BIG2_CAPACITY			930
20#endif /* TARGET_FLAVOUR_FPGA */
21#define BIG_CAPACITY			1024
22
23#define MHU_TX_ADDR			45000000 /* hex */
24#define MHU_TX_COMPAT			"arm,mhuv2-tx","arm,primecell"
25#define MHU_TX_INT_NAME			"mhu_tx"
26
27#define MHU_RX_ADDR			45010000 /* hex */
28#define MHU_RX_COMPAT			"arm,mhuv2-rx","arm,primecell"
29#define MHU_OFFSET			0x1000
30#define MHU_MBOX_CELLS			2
31#define MHU_RX_INT_NUM			317
32#define MHU_RX_INT_NAME			"mhu_rx"
33
34#define LIT_CPU_PMU_COMPATIBLE		"arm,cortex-a520-pmu"
35#define MID_CPU_PMU_COMPATIBLE		"arm,cortex-a720-pmu"
36#define BIG_CPU_PMU_COMPATIBLE		"arm,cortex-x4-pmu"
37
38#define MPAM_ADDR			0x1 0x00010000 /* 0x1_0001_0000 */
39#define UARTCLK_FREQ			5000000
40
41#define DPU_ADDR			2cc00000
42#define DPU_IRQ				69
43
44#define ETHERNET_ADDR			18000000
45#define ETHERNET_INT			109
46
47#define SYS_REGS_ADDR			1c010000
48
49#define MMC_ADDR			1c050000
50#define MMC_INT_0			107
51#define MMC_INT_1			108
52
53#define RTC_ADDR			1c170000
54#define RTC_INT				100
55
56#define KMI_0_ADDR			1c060000
57#define KMI_0_INT			197
58#define KMI_1_ADDR			1c070000
59#define KMI_1_INT			103
60
61#define VIRTIO_BLOCK_ADDR		1c130000
62#define VIRTIO_BLOCK_INT		204
63
64#include "tc-common.dtsi"
65#if TARGET_FLAVOUR_FVP
66#include "tc-fvp.dtsi"
67#else
68#include "tc-fpga.dtsi"
69#endif /* TARGET_FLAVOUR_FVP */
70#include "tc-base.dtsi"
71
72/ {
73	cpus {
74#if TARGET_FLAVOUR_FPGA
75		cpu-map {
76			cluster0 {
77				core8 {
78					cpu = <&CPU8>;
79				};
80				core9 {
81					cpu = <&CPU9>;
82				};
83				core10 {
84					cpu = <&CPU10>;
85				};
86				core11 {
87					cpu = <&CPU11>;
88				};
89				core12 {
90					cpu = <&CPU12>;
91				};
92				core13 {
93					cpu = <&CPU13>;
94				};
95			};
96		};
97#endif
98
99		CPU2:cpu@200 {
100			clocks = <&scmi_dvfs 0>;
101			capacity-dmips-mhz = <LIT_CAPACITY>;
102		};
103
104		CPU3:cpu@300 {
105			clocks = <&scmi_dvfs 0>;
106			capacity-dmips-mhz = <LIT_CAPACITY>;
107		};
108
109		CPU6:cpu@600 {
110			clocks = <&scmi_dvfs 1>;
111			capacity-dmips-mhz = <MID_CAPACITY>;
112		};
113
114		CPU7:cpu@700 {
115			clocks = <&scmi_dvfs 1>;
116			capacity-dmips-mhz = <MID_CAPACITY>;
117		};
118
119#if TARGET_FLAVOUR_FPGA
120		CPU8:cpu@800 {
121			device_type = "cpu";
122			compatible = "arm,armv8";
123			reg = <0x800>;
124			enable-method = "psci";
125			clocks = <&scmi_dvfs 1>;
126			capacity-dmips-mhz = <MID_CAPACITY>;
127			amu = <&amu>;
128			supports-mpmm;
129		};
130
131		CPU9:cpu@900 {
132			device_type = "cpu";
133			compatible = "arm,armv8";
134			reg = <0x900>;
135			enable-method = "psci";
136			clocks = <&scmi_dvfs 2>;
137			capacity-dmips-mhz = <BIG2_CAPACITY>;
138			amu = <&amu>;
139			supports-mpmm;
140		};
141
142		CPU10:cpu@A00 {
143			device_type = "cpu";
144			compatible = "arm,armv8";
145			reg = <0xA00>;
146			enable-method = "psci";
147			clocks = <&scmi_dvfs 2>;
148			capacity-dmips-mhz = <BIG2_CAPACITY>;
149			amu = <&amu>;
150			supports-mpmm;
151		};
152
153		CPU11:cpu@B00 {
154			device_type = "cpu";
155			compatible = "arm,armv8";
156			reg = <0xB00>;
157			enable-method = "psci";
158			clocks = <&scmi_dvfs 2>;
159			capacity-dmips-mhz = <BIG2_CAPACITY>;
160			amu = <&amu>;
161			supports-mpmm;
162		};
163
164		CPU12:cpu@C00 {
165			device_type = "cpu";
166			compatible = "arm,armv8";
167			reg = <0xC00>;
168			enable-method = "psci";
169			clocks = <&scmi_dvfs 3>;
170			capacity-dmips-mhz = <BIG_CAPACITY>;
171			amu = <&amu>;
172			supports-mpmm;
173		};
174
175		CPU13:cpu@D00 {
176			device_type = "cpu";
177			compatible = "arm,armv8";
178			reg = <0xD00>;
179			enable-method = "psci";
180			clocks = <&scmi_dvfs 3>;
181			capacity-dmips-mhz = <BIG_CAPACITY>;
182			amu = <&amu>;
183			supports-mpmm;
184		};
185#endif
186	};
187
188#if TARGET_FLAVOUR_FPGA
189	ete8 {
190		compatible = "arm,embedded-trace-extension";
191		cpu = <&CPU8>;
192	};
193
194	ete9 {
195		compatible = "arm,embedded-trace-extension";
196		cpu = <&CPU9>;
197	};
198
199	ete10 {
200		compatible = "arm,embedded-trace-extension";
201		cpu = <&CPU10>;
202	};
203
204	ete11 {
205		compatible = "arm,embedded-trace-extension";
206		cpu = <&CPU11>;
207	};
208
209	ete12 {
210		compatible = "arm,embedded-trace-extension";
211		cpu = <&CPU12>;
212	};
213
214	ete13 {
215		compatible = "arm,embedded-trace-extension";
216		cpu = <&CPU13>;
217	};
218#endif /* TARGET_FLAVOUR_FPGA */
219
220	cmn-pmu {
221		compatible = "arm,ci-700";
222		reg = <0x0 0x50000000 0x0 0x10000000>;
223		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
224	};
225
226	mbox_db_rx: mhu@MHU_RX_ADDR {
227		arm,mhuv2-protocols = <0 1>;
228	};
229
230	mbox_db_tx: mhu@MHU_TX_ADDR {
231		arm,mhuv2-protocols = <0 1>;
232	};
233
234	firmware {
235		/*
236		 * TC2 does not have a P2A channel, but wiring one was needed to make Linux work
237		 * (by chance). At the time the SCMI driver did not support bidirectional
238		 * mailboxes so as a workaround, the A2P channel was wired for TX communication
239		 * and the synchronous replies would be read asyncrhonously as if coming from
240		 * the P2A channel, while being the actual A2P channel.
241		 *
242		 * This will not work with kernels > 5.15, but keep it around to keep TC2
243		 * working with its target kernel. Newer kernels will still work, but SCMI
244		 * won't as they check that the two regions are distinct.
245		 */
246		scmi {
247			mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
248			shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
249		};
250	};
251
252	gic: interrupt-controller@GIC_CTRL_ADDR {
253		ppi-partitions {
254			ppi_partition_little: interrupt-partition-0 {
255				affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
256			};
257
258#if TARGET_FLAVOUR_FVP
259			ppi_partition_mid: interrupt-partition-1 {
260				affinity = <&CPU4>, <&CPU5>, <&CPU6>;
261			};
262
263			ppi_partition_big: interrupt-partition-2 {
264				affinity = <&CPU7>;
265			};
266#elif TARGET_FLAVOUR_FPGA
267			ppi_partition_mid: interrupt-partition-1 {
268				affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
269			};
270
271			ppi_partition_big: interrupt-partition-2 {
272				affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
273			};
274#endif
275		};
276	};
277
278	spe-pmu-big {
279		status = "okay";
280	};
281
282	smmu_700: iommu@3f000000 {
283		status = "okay";
284	};
285
286	dp0: display@DPU_ADDR {
287#if TC_SCMI_PD_CTRL_EN
288		power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
289#endif
290		iommus = <&smmu_700 0x100>;
291	};
292
293	gpu: gpu@2d000000 {
294		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
295			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
296			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
297		interrupt-names = "JOB", "MMU", "GPU";
298		iommus = <&smmu_700 0x200>;
299	};
300};
301