1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL1_H 8 #define CONTEXT_EL1_H 9 10 #include <lib/extensions/sysreg128.h> 11 12 #ifndef __ASSEMBLER__ 13 14 /******************************************************************************* 15 * EL1 Registers: 16 * AArch64 EL1 system register context structure for preserving the 17 * architectural state during world switches. 18 ******************************************************************************/ 19 20 typedef struct el1_common_regs { 21 uint64_t spsr_el1; 22 uint64_t elr_el1; 23 24 #if (!ERRATA_SPECULATIVE_AT) 25 uint64_t sctlr_el1; 26 uint64_t tcr_el1; 27 #endif /* ERRATA_SPECULATIVE_AT=0 */ 28 29 uint64_t cpacr_el1; 30 uint64_t csselr_el1; 31 uint64_t sp_el1; 32 uint64_t esr_el1; 33 uint64_t mair_el1; 34 uint64_t amair_el1; 35 uint64_t actlr_el1; 36 uint64_t tpidr_el1; 37 uint64_t tpidr_el0; 38 uint64_t tpidrro_el0; 39 uint64_t far_el1; 40 uint64_t afsr0_el1; 41 uint64_t afsr1_el1; 42 uint64_t contextidr_el1; 43 uint64_t vbar_el1; 44 uint64_t mdccint_el1; 45 uint64_t mdscr_el1; 46 sysreg_t par_el1; 47 sysreg_t ttbr0_el1; 48 sysreg_t ttbr1_el1; 49 } el1_common_regs_t; 50 51 typedef struct el1_aarch32_regs { 52 uint64_t spsr_abt; 53 uint64_t spsr_und; 54 uint64_t spsr_irq; 55 uint64_t spsr_fiq; 56 uint64_t dacr32_el2; 57 uint64_t ifsr32_el2; 58 } el1_aarch32_regs_t; 59 60 typedef struct el1_arch_timer_regs { 61 uint64_t cntp_ctl_el0; 62 uint64_t cntp_cval_el0; 63 uint64_t cntv_ctl_el0; 64 uint64_t cntv_cval_el0; 65 uint64_t cntkctl_el1; 66 } el1_arch_timer_regs_t; 67 68 typedef struct el1_mte2_regs { 69 uint64_t tfsre0_el1; 70 uint64_t tfsr_el1; 71 uint64_t rgsr_el1; 72 uint64_t gcr_el1; 73 } el1_mte2_regs_t; 74 75 typedef struct el1_ras_regs { 76 uint64_t disr_el1; 77 } el1_ras_regs_t; 78 79 typedef struct el1_s1pie_regs { 80 uint64_t pire0_el1; 81 uint64_t pir_el1; 82 } el1_s1pie_regs_t; 83 84 typedef struct el1_s1poe_regs { 85 uint64_t por_el1; 86 } el1_s1poe_regs_t; 87 88 typedef struct el1_s2poe_regs { 89 uint64_t s2por_el1; 90 } el1_s2poe_regs_t; 91 92 typedef struct el1_tcr2_regs { 93 uint64_t tcr2_el1; 94 } el1_tcr2_regs_t; 95 96 typedef struct el1_trf_regs { 97 uint64_t trfcr_el1; 98 } el1_trf_regs_t; 99 100 typedef struct el1_csv2_2_regs { 101 uint64_t scxtnum_el0; 102 uint64_t scxtnum_el1; 103 } el1_csv2_2_regs_t; 104 105 typedef struct el1_gcs_regs { 106 uint64_t gcscr_el1; 107 uint64_t gcscre0_el1; 108 uint64_t gcspr_el1; 109 uint64_t gcspr_el0; 110 } el1_gcs_regs_t; 111 112 typedef struct el1_the_regs { 113 sysreg_t rcwmask_el1; 114 sysreg_t rcwsmask_el1; 115 } el1_the_regs_t; 116 117 typedef struct el1_sctlr2_regs { 118 uint64_t sctlr2_el1; 119 } el1_sctlr2_regs_t; 120 121 typedef struct el1_ls64_regs { 122 uint64_t accdata_el1; 123 } el1_ls64_regs_t; 124 125 typedef struct el1_sysregs { 126 127 el1_common_regs_t common; 128 129 #if CTX_INCLUDE_AARCH32_REGS 130 el1_aarch32_regs_t el1_aarch32; 131 #endif 132 133 #if NS_TIMER_SWITCH 134 el1_arch_timer_regs_t arch_timer; 135 #endif 136 137 #if ENABLE_FEAT_MTE2 138 el1_mte2_regs_t mte2; 139 #endif 140 141 #if ENABLE_FEAT_RAS 142 el1_ras_regs_t ras; 143 #endif 144 145 #if ENABLE_FEAT_S1PIE 146 el1_s1pie_regs_t s1pie; 147 #endif 148 149 #if ENABLE_FEAT_S1POE 150 el1_s1poe_regs_t s1poe; 151 #endif 152 153 #if ENABLE_FEAT_S2POE 154 el1_s2poe_regs_t s2poe; 155 #endif 156 157 #if ENABLE_FEAT_TCR2 158 el1_tcr2_regs_t tcr2; 159 #endif 160 161 #if ENABLE_TRF_FOR_NS 162 el1_trf_regs_t trf; 163 #endif 164 165 #if ENABLE_FEAT_CSV2_2 166 el1_csv2_2_regs_t csv2_2; 167 #endif 168 169 #if ENABLE_FEAT_GCS 170 el1_gcs_regs_t gcs; 171 #endif 172 173 #if ENABLE_FEAT_THE 174 el1_the_regs_t the; 175 #endif 176 177 #if ENABLE_FEAT_SCTLR2 178 el1_sctlr2_regs_t sctlr2; 179 #endif 180 181 #if ENABLE_FEAT_LS64_ACCDATA 182 el1_ls64_regs_t ls64; 183 #endif 184 } el1_sysregs_t; 185 186 187 /* 188 * Macros to access members related to individual features of the el1_sysregs_t 189 * structures. 190 */ 191 192 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) 193 194 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 195 = (uint64_t) (val)) 196 197 #if NS_TIMER_SWITCH 198 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) 199 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ 200 = (uint64_t) (val)) 201 #else 202 #define read_el1_ctx_arch_timer(ctx, reg) ULL(0) 203 #define write_el1_ctx_arch_timer(ctx, reg, val) 204 #endif /* NS_TIMER_SWITCH */ 205 206 #if CTX_INCLUDE_AARCH32_REGS 207 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) 208 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ 209 = (uint64_t) (val)) 210 #else 211 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) 212 #define write_el1_ctx_aarch32(ctx, reg, val) 213 #endif /* CTX_INCLUDE_AARCH32_REGS */ 214 215 #if ENABLE_FEAT_MTE2 216 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 217 #define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 218 = (uint64_t) (val)) 219 #else 220 #define read_el1_ctx_mte2(ctx, reg) ULL(0) 221 #define write_el1_ctx_mte2(ctx, reg, val) 222 #endif /* ENABLE_FEAT_MTE2 */ 223 224 #if ENABLE_FEAT_RAS 225 #define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg) 226 #define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 227 = (uint64_t) (val)) 228 #else 229 #define read_el1_ctx_ras(ctx, reg) ULL(0) 230 #define write_el1_ctx_ras(ctx, reg, val) 231 #endif /* ENABLE_FEAT_RAS */ 232 233 #if ENABLE_FEAT_S1PIE 234 #define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg) 235 #define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \ 236 = (uint64_t) (val)) 237 #else 238 #define read_el1_ctx_s1pie(ctx, reg) ULL(0) 239 #define write_el1_ctx_s1pie(ctx, reg, val) 240 #endif /* ENABLE_FEAT_S1PIE */ 241 242 #if ENABLE_FEAT_S1POE 243 #define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg) 244 #define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \ 245 = (uint64_t) (val)) 246 #else 247 #define read_el1_ctx_s1poe(ctx, reg) ULL(0) 248 #define write_el1_ctx_s1poe(ctx, reg, val) 249 #endif /* ENABLE_FEAT_S1POE */ 250 251 #if ENABLE_FEAT_S2POE 252 #define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg) 253 #define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \ 254 = (uint64_t) (val)) 255 #else 256 #define read_el1_ctx_s2poe(ctx, reg) ULL(0) 257 #define write_el1_ctx_s2poe(ctx, reg, val) 258 #endif /* ENABLE_FEAT_S2POE */ 259 260 #if ENABLE_FEAT_TCR2 261 #define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 262 #define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 263 = (uint64_t) (val)) 264 #else 265 #define read_el1_ctx_tcr2(ctx, reg) ULL(0) 266 #define write_el1_ctx_tcr2(ctx, reg, val) 267 #endif /* ENABLE_FEAT_TCR2 */ 268 269 #if ENABLE_TRF_FOR_NS 270 #define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg) 271 #define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 272 = (uint64_t) (val)) 273 #else 274 #define read_el1_ctx_trf(ctx, reg) ULL(0) 275 #define write_el1_ctx_trf(ctx, reg, val) 276 #endif /* ENABLE_TRF_FOR_NS */ 277 278 #if ENABLE_FEAT_CSV2_2 279 #define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg) 280 #define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \ 281 = (uint64_t) (val)) 282 #else 283 #define read_el1_ctx_csv2_2(ctx, reg) ULL(0) 284 #define write_el1_ctx_csv2_2(ctx, reg, val) 285 #endif /* ENABLE_FEAT_CSV2_2 */ 286 287 #if ENABLE_FEAT_GCS 288 #define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 289 #define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 290 = (uint64_t) (val)) 291 #else 292 #define read_el1_ctx_gcs(ctx, reg) ULL(0) 293 #define write_el1_ctx_gcs(ctx, reg, val) 294 #endif /* ENABLE_FEAT_GCS */ 295 296 #if ENABLE_FEAT_THE 297 #define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg) 298 #define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \ 299 = (uint64_t) (val)) 300 #else 301 #define read_el1_ctx_the(ctx, reg) ULL(0) 302 #define write_el1_ctx_the(ctx, reg, val) 303 #endif /* ENABLE_FEAT_THE */ 304 305 #if ENABLE_FEAT_SCTLR2 306 #define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 307 #define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 308 = (uint64_t) (val)) 309 #else 310 #define read_el1_ctx_sctlr2(ctx, reg) ULL(0) 311 #define write_el1_ctx_sctlr2(ctx, reg, val) 312 #endif /* ENABLE_FEAT_SCTLR2 */ 313 314 #if ENABLE_FEAT_LS64_ACCDATA 315 #define read_el1_ctx_ls64(ctx, reg) (((ctx)->ls64).reg) 316 #define write_el1_ctx_ls64(ctx, reg, val) ((((ctx)->ls64).reg) \ 317 = (uint64_t) (val)) 318 #else 319 #define read_el1_ctx_ls64(ctx, reg) ULL(0) 320 #define write_el1_ctx_ls64(ctx, reg, val) 321 #endif /* ENABLE_FEAT_LS64_ACCDATA */ 322 /******************************************************************************/ 323 #endif /* __ASSEMBLER__ */ 324 325 #endif /* CONTEXT_EL1_H */ 326