1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <plat_common.h> 13 #include "versal_def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #define PLATFORM_STACK_SIZE U(0x440) 21 22 #define PLATFORM_CORE_COUNT U(2) 23 #define PLAT_MAX_PWR_LVL U(1) 24 #define PLAT_MAX_RET_STATE U(1) 25 #define PLAT_MAX_OFF_STATE U(2) 26 27 /******************************************************************************* 28 * BL31 specific defines. 29 ******************************************************************************/ 30 /* 31 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 32 * present). BL31_BASE is calculated using the current BL31 debug size plus a 33 * little space for growth. 34 */ 35 #ifndef VERSAL_ATF_MEM_BASE 36 # define BL31_BASE U(0xfffe0000) 37 # define BL31_LIMIT U(0x100000000) 38 #else 39 # define BL31_BASE U(VERSAL_ATF_MEM_BASE) 40 # define BL31_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE) 41 # ifdef VERSAL_ATF_MEM_PROGBITS_SIZE 42 # define BL31_PROGBITS_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE) 43 # endif 44 #endif 45 46 /******************************************************************************* 47 * BL32 specific defines. 48 ******************************************************************************/ 49 #ifndef VERSAL_BL32_MEM_BASE 50 # define BL32_BASE U(0x60000000) 51 # define BL32_LIMIT U(0x80000000) 52 #else 53 # define BL32_BASE U(VERSAL_BL32_MEM_BASE) 54 # define BL32_LIMIT U(VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE) 55 #endif 56 57 /******************************************************************************* 58 * BL33 specific defines. 59 ******************************************************************************/ 60 #ifndef PRELOADED_BL33_BASE 61 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 62 #else 63 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 64 #endif 65 66 /******************************************************************************* 67 * TSP specific defines. 68 ******************************************************************************/ 69 #define TSP_SEC_MEM_BASE BL32_BASE 70 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 71 72 /* ID of the secure physical generic timer interrupt used by the TSP */ 73 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 74 75 /******************************************************************************* 76 * Platform specific page table and MMU setup constants 77 ******************************************************************************/ 78 79 #if (BL31_BASE >= (1ULL << 32U)) 80 /* Address range in High DDR and HBM memory range */ 81 #define PLAT_ADDR_SPACE_SHIFT U(42) 82 #else 83 /* Address range in OCM and Low DDR memory range */ 84 #define PLAT_ADDR_SPACE_SHIFT U(32) 85 #endif 86 87 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << PLAT_ADDR_SPACE_SHIFT) 88 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << PLAT_ADDR_SPACE_SHIFT) 89 90 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 91 92 #define PLAT_OCM_BASE U(0xFFFE0000) 93 #define PLAT_OCM_LIMIT U(0xFFFFFFFF) 94 95 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 96 97 #ifndef MAX_MMAP_REGIONS 98 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 99 #define MAX_MMAP_REGIONS 9 100 #else 101 #define MAX_MMAP_REGIONS 8 102 #endif 103 #endif 104 105 #ifndef MAX_XLAT_TABLES 106 #if !IS_TFA_IN_OCM(BL31_BASE) 107 #define MAX_XLAT_TABLES 9 108 #else 109 #define MAX_XLAT_TABLES 5 110 #endif 111 #endif 112 113 #define CACHE_WRITEBACK_SHIFT 6 114 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 115 116 #define PLAT_ARM_GICD_BASE U(0xF9000000) 117 #define PLAT_ARM_GICR_BASE U(0xF9080000) 118 119 /* 120 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 121 * terminology. On a GICv2 system or mode, the lists will be merged and treated 122 * as Group 0 interrupts. 123 */ 124 #define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER 125 #define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER 126 #define PLAT_VERSAL_IPI_IRQ U(62) 127 128 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \ 129 INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 130 GIC_INTR_CFG_LEVEL) 131 132 #define PLAT_VERSAL_G0_IRQ_PROPS(grp) \ 133 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 134 GIC_INTR_CFG_EDGE), \ 135 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_EDGE) 137 138 #define IRQ_MAX 142U 139 140 #endif /* PLATFORM_DEF_H */ 141