1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_none 0 22 #define VERSAL_CONSOLE_ID_pl011 1 23 #define VERSAL_CONSOLE_ID_pl011_0 1 24 #define VERSAL_CONSOLE_ID_pl011_1 2 25 #define VERSAL_CONSOLE_ID_dcc 3 26 #define VERSAL_CONSOLE_ID_dtb 4 27 28 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 29 30 /* Runtime console */ 31 #define RT_CONSOLE_ID_pl011 1 32 #define RT_CONSOLE_ID_pl011_0 1 33 #define RT_CONSOLE_ID_pl011_1 2 34 #define RT_CONSOLE_ID_dcc 3 35 #define RT_CONSOLE_ID_dtb 4 36 37 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 38 39 /* List of platforms */ 40 #define VERSAL_SILICON U(0) 41 #define VERSAL_SPP U(1) 42 #define VERSAL_EMU U(2) 43 #define VERSAL_QEMU U(3) 44 #define VERSAL_COSIM U(7) 45 46 /* Firmware Image Package */ 47 #define VERSAL_PRIMARY_CPU 0 48 49 /******************************************************************************* 50 * memory map related constants 51 ******************************************************************************/ 52 #define DEVICE0_BASE 0xFF000000 53 #define DEVICE0_SIZE 0x00E00000 54 #define DEVICE1_BASE 0xF9000000 55 #define DEVICE1_SIZE 0x00800000 56 57 /******************************************************************************* 58 * IRQ constants 59 ******************************************************************************/ 60 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 61 #define ARM_IRQ_SEC_PHY_TIMER 29 62 63 /******************************************************************************* 64 * CCI-400 related constants 65 ******************************************************************************/ 66 #define PLAT_ARM_CCI_BASE 0xFD000000 67 #define PLAT_ARM_CCI_SIZE 0x00100000 68 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 69 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 70 71 /******************************************************************************* 72 * UART related constants 73 ******************************************************************************/ 74 #define VERSAL_UART0_BASE 0xFF000000 75 #define VERSAL_UART1_BASE 0xFF010000 76 77 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 78 # define UART_BASE VERSAL_UART0_BASE 79 # define UART_TYPE CONSOLE_PL011 80 #elif CONSOLE_IS(pl011_1) 81 # define UART_BASE VERSAL_UART1_BASE 82 # define UART_TYPE CONSOLE_PL011 83 #elif CONSOLE_IS(dcc) 84 # define UART_BASE 0x0 85 # define UART_TYPE CONSOLE_DCC 86 #elif CONSOLE_IS(none) 87 # define UART_TYPE CONSOLE_NONE 88 #else 89 # error "invalid VERSAL_CONSOLE" 90 #endif 91 92 /* Runtime console */ 93 #if defined(CONSOLE_RUNTIME) 94 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 95 # define RT_UART_BASE VERSAL_UART0_BASE 96 # define RT_UART_TYPE CONSOLE_PL011 97 #elif RT_CONSOLE_IS(pl011_1) 98 # define RT_UART_BASE VERSAL_UART1_BASE 99 # define RT_UART_TYPE CONSOLE_PL011 100 #elif RT_CONSOLE_IS(dcc) 101 # define RT_UART_BASE 0x0 102 # define RT_UART_TYPE CONSOLE_DCC 103 #else 104 # error "invalid CONSOLE_RUNTIME" 105 #endif 106 #endif 107 108 /******************************************************************************* 109 * Platform related constants 110 ******************************************************************************/ 111 #define UART_BAUDRATE 115200 112 113 /* Access control register defines */ 114 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 115 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 116 117 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 118 #define CRF_BASE 0xFD1A0000 119 #define CRF_SIZE 0x00600000 120 121 /* CRF registers and bitfields */ 122 #define CRF_RST_APU (CRF_BASE + 0X00000300) 123 124 #define CRF_RST_APU_ACPU_RESET (1 << 0) 125 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 126 127 /* IOU SCNTRS */ 128 #define IOU_SCNTRS_BASE U(0xFF140000) 129 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 130 131 /* APU registers and bitfields */ 132 #define FPD_APU_BASE 0xFD5C0000U 133 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 134 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 135 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 136 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 137 138 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 139 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 140 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 141 142 /* PMC registers and bitfields */ 143 #define PMC_GLOBAL_BASE 0xF1110000U 144 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 145 146 #endif /* VERSAL_DEF_H */ 147