1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004 Texas Insturments
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2002
10 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 */
12
13 /*
14 * CPU specific code
15 */
16
17 #include <common.h>
18 #include <command.h>
19 #include <cpu_func.h>
20 #include <irq_func.h>
21 #include <asm/cache.h>
22 #include <asm/system.h>
23 #include <asm/arm11.h>
24
25 static void cache_flush(void);
26
cleanup_before_linux(void)27 int cleanup_before_linux (void)
28 {
29 /*
30 * this function is called just before we call linux
31 * it prepares the processor for linux
32 *
33 * we turn off caches etc ...
34 */
35
36 disable_interrupts();
37
38 /* turn off I/D-cache */
39 icache_disable();
40 dcache_disable();
41 /* flush I/D-cache */
42 cache_flush();
43
44 return 0;
45 }
46
allow_unaligned(void)47 void allow_unaligned(void)
48 {
49 arm11_arch_cp15_allow_unaligned();
50 }
51
cache_flush(void)52 static void cache_flush(void)
53 {
54 unsigned long i = 0;
55 /* clean entire data cache */
56 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
57 /* invalidate both caches and flush btb */
58 asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
59 /* mem barrier to sync things */
60 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
61 }
62
63 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
invalidate_dcache_all(void)64 void invalidate_dcache_all(void)
65 {
66 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
67 }
68
flush_dcache_all(void)69 void flush_dcache_all(void)
70 {
71 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
72 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
73 }
74
invalidate_dcache_range(unsigned long start,unsigned long stop)75 void invalidate_dcache_range(unsigned long start, unsigned long stop)
76 {
77 if (!check_cache_range(start, stop))
78 return;
79
80 while (start < stop) {
81 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
82 start += CONFIG_SYS_CACHELINE_SIZE;
83 }
84 }
85
flush_dcache_range(unsigned long start,unsigned long stop)86 void flush_dcache_range(unsigned long start, unsigned long stop)
87 {
88 if (!check_cache_range(start, stop))
89 return;
90
91 while (start < stop) {
92 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
93 start += CONFIG_SYS_CACHELINE_SIZE;
94 }
95
96 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
97 }
98
99 #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
invalidate_dcache_all(void)100 void invalidate_dcache_all(void)
101 {
102 }
103
flush_dcache_all(void)104 void flush_dcache_all(void)
105 {
106 }
107 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
108
109 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches(void)110 void enable_caches(void)
111 {
112 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
113 icache_enable();
114 #endif
115 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
116 dcache_enable();
117 #endif
118 }
119 #endif
120