1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
5 */
6
7 #include <common.h>
8 #include <clock_legacy.h>
9 #include <cpu_func.h>
10 #include <env.h>
11 #include <fsl_immap.h>
12 #include <fsl_ifc.h>
13 #include <init.h>
14 #include <linux/sizes.h>
15 #include <log.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/cache.h>
19 #include <asm/io.h>
20 #include <asm/global_data.h>
21 #include <asm/arch-fsl-layerscape/config.h>
22 #include <asm/arch-fsl-layerscape/ns_access.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
24 #include <asm/gic-v3.h>
25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
26 #include <fsl_csu.h>
27 #endif
28 #ifdef CONFIG_SYS_FSL_DDR
29 #include <fsl_ddr_sdram.h>
30 #include <fsl_ddr.h>
31 #endif
32 #ifdef CONFIG_CHAIN_OF_TRUST
33 #include <fsl_validate.h>
34 #endif
35 #include <fsl_immap.h>
36 #include <dm.h>
37 #include <dm/device_compat.h>
38 #include <linux/err.h>
39 #ifdef CONFIG_GIC_V3_ITS
40 DECLARE_GLOBAL_DATA_PTR;
41 #endif
42
43 #ifdef CONFIG_GIC_V3_ITS
44 #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
45 #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
46 #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
47 PROPTABLE_MAX_SZ, SZ_1M)
fdt_add_resv_mem_gic_rd_tables(void * blob,u64 base,size_t size)48 static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
49 {
50 int err;
51 struct fdt_memory gic_rd_tables;
52
53 gic_rd_tables.start = base;
54 gic_rd_tables.end = base + size - 1;
55 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
56 NULL, 0, NULL, 0);
57 if (err < 0)
58 debug("%s: failed to add reserved memory: %d\n", __func__, err);
59
60 return err;
61 }
62
ls_gic_rd_tables_init(void * blob)63 int ls_gic_rd_tables_init(void *blob)
64 {
65 u64 gic_lpi_base;
66 int ret;
67
68 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
69 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
70 if (ret)
71 return ret;
72
73 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
74 if (ret)
75 debug("%s: failed to init gic-lpi-tables\n", __func__);
76
77 return ret;
78 }
79 #endif
80
soc_has_dp_ddr(void)81 bool soc_has_dp_ddr(void)
82 {
83 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
84 u32 svr = gur_in32(&gur->svr);
85
86 /* LS2085A, LS2088A, LS2048A has DP_DDR */
87 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
88 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
89 (SVR_SOC_VER(svr) == SVR_LS2048A))
90 return true;
91
92 return false;
93 }
94
soc_has_aiop(void)95 bool soc_has_aiop(void)
96 {
97 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
98 u32 svr = gur_in32(&gur->svr);
99
100 /* LS2085A has AIOP */
101 if (SVR_SOC_VER(svr) == SVR_LS2085A)
102 return true;
103
104 return false;
105 }
106
set_usb_txvreftune(u32 __iomem * scfg,u32 offset)107 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
108 {
109 scfg_clrsetbits32(scfg + offset / 4,
110 0xF << 6,
111 SCFG_USB_TXVREFTUNE << 6);
112 }
113
erratum_a009008(void)114 static void erratum_a009008(void)
115 {
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
117 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
118
119 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
120 defined(CONFIG_ARCH_LS1012A)
121 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
123 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
124 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
125 #endif
126 #elif defined(CONFIG_ARCH_LS2080A)
127 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
128 #endif
129 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
130 }
131
set_usb_sqrxtune(u32 __iomem * scfg,u32 offset)132 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
133 {
134 scfg_clrbits32(scfg + offset / 4,
135 SCFG_USB_SQRXTUNE_MASK << 23);
136 }
137
erratum_a009798(void)138 static void erratum_a009798(void)
139 {
140 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
141 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
142
143 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
144 defined(CONFIG_ARCH_LS1012A)
145 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
146 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
147 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
148 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
149 #endif
150 #elif defined(CONFIG_ARCH_LS2080A)
151 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
152 #endif
153 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
154 }
155
156 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
157 defined(CONFIG_ARCH_LS1012A)
set_usb_pcstxswingfull(u32 __iomem * scfg,u32 offset)158 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
159 {
160 scfg_clrsetbits32(scfg + offset / 4,
161 0x7F << 9,
162 SCFG_USB_PCSTXSWINGFULL << 9);
163 }
164 #endif
165
erratum_a008997(void)166 static void erratum_a008997(void)
167 {
168 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
169 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
170 defined(CONFIG_ARCH_LS1012A)
171 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
172
173 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
174 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
175 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
176 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
177 #endif
178 #elif defined(CONFIG_ARCH_LS1028A)
179 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
180 0x7F << 11,
181 DCSR_USB_PCSTXSWINGFULL << 11);
182 #endif
183 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
184 }
185
186 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
187 defined(CONFIG_ARCH_LS1012A)
188
189 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
190 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
193 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
194
195 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
196 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
197 defined(CONFIG_ARCH_LX2162A)
198
199 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
202 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
203 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
204
205 #endif
206
erratum_a009007(void)207 static void erratum_a009007(void)
208 {
209 if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
210 return;
211
212 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
213 defined(CONFIG_ARCH_LS1012A)
214 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
215
216 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
217 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
218 usb_phy = (void __iomem *)SCFG_USB_PHY2;
219 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
220
221 usb_phy = (void __iomem *)SCFG_USB_PHY3;
222 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
223 #endif
224 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
225 defined(CONFIG_ARCH_LS1028A)
226 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
227
228 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
229 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
230 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
231 }
232
233 #if defined(CONFIG_FSL_LSCH3)
erratum_a050204(void)234 static void erratum_a050204(void)
235 {
236 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
237 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
238
239 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
240 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
241 #endif
242 }
243 /*
244 * This erratum requires setting a value to eddrtqcr1 to
245 * optimal the DDR performance.
246 */
erratum_a008336(void)247 static void erratum_a008336(void)
248 {
249 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
250 u32 *eddrtqcr1;
251
252 #ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
253 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
254 if (fsl_ddr_get_version(0) == 0x50200)
255 out_le32(eddrtqcr1, 0x63b30002);
256 #endif
257 #ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
258 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
259 if (fsl_ddr_get_version(0) == 0x50200)
260 out_le32(eddrtqcr1, 0x63b30002);
261 #endif
262 #endif
263 }
264
265 /*
266 * This erratum requires a register write before being Memory
267 * controller 3 being enabled.
268 */
erratum_a008514(void)269 static void erratum_a008514(void)
270 {
271 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
272 u32 *eddrtqcr1;
273
274 #ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
275 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
276 out_le32(eddrtqcr1, 0x63b20002);
277 #endif
278 #endif
279 }
280 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
281 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
282
get_internval_val_mhz(void)283 static unsigned long get_internval_val_mhz(void)
284 {
285 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
286 /*
287 * interval is the number of platform cycles(MHz) between
288 * wake up events generated by EPU.
289 */
290 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
291
292 if (interval)
293 interval_mhz = dectoul(interval, NULL);
294
295 return interval_mhz;
296 }
297
erratum_a009635(void)298 void erratum_a009635(void)
299 {
300 u32 val;
301 unsigned long interval_mhz = get_internval_val_mhz();
302
303 if (!interval_mhz)
304 return;
305
306 val = in_le32(DCSR_CGACRE5);
307 writel(val | 0x00000200, DCSR_CGACRE5);
308
309 val = in_le32(EPU_EPCMPR5);
310 writel(interval_mhz, EPU_EPCMPR5);
311 val = in_le32(EPU_EPCCR5);
312 writel(val | 0x82820000, EPU_EPCCR5);
313 val = in_le32(EPU_EPSMCR5);
314 writel(val | 0x002f0000, EPU_EPSMCR5);
315 val = in_le32(EPU_EPECR5);
316 writel(val | 0x20000000, EPU_EPECR5);
317 val = in_le32(EPU_EPGCR);
318 writel(val | 0x80000000, EPU_EPGCR);
319 }
320 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
321
erratum_rcw_src(void)322 static void erratum_rcw_src(void)
323 {
324 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
325 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
326 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
327 u32 val;
328
329 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
330 val &= ~DCFG_PORSR1_RCW_SRC;
331 val |= DCFG_PORSR1_RCW_SRC_NOR;
332 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
333 #endif
334 }
335
336 #define I2C_DEBUG_REG 0x6
337 #define I2C_GLITCH_EN 0x8
338 /*
339 * This erratum requires setting glitch_en bit to enable
340 * digital glitch filter to improve clock stability.
341 */
342 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203(void)343 static void erratum_a009203(void)
344 {
345 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
346 u8 __iomem *ptr;
347 #ifdef I2C1_BASE_ADDR
348 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
349
350 writeb(I2C_GLITCH_EN, ptr);
351 #endif
352 #ifdef I2C2_BASE_ADDR
353 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
354
355 writeb(I2C_GLITCH_EN, ptr);
356 #endif
357 #ifdef I2C3_BASE_ADDR
358 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
359
360 writeb(I2C_GLITCH_EN, ptr);
361 #endif
362 #ifdef I2C4_BASE_ADDR
363 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
364
365 writeb(I2C_GLITCH_EN, ptr);
366 #endif
367 #endif
368 }
369 #endif
370
bypass_smmu(void)371 void bypass_smmu(void)
372 {
373 u32 val;
374 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
375 out_le32(SMMU_SCR0, val);
376 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
377 out_le32(SMMU_NSCR0, val);
378 }
fsl_lsch3_early_init_f(void)379 void fsl_lsch3_early_init_f(void)
380 {
381 erratum_rcw_src();
382 #ifdef CONFIG_FSL_IFC
383 init_early_memctl_regs(); /* tighten IFC timing */
384 #endif
385 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
386 erratum_a009203();
387 #endif
388 erratum_a008514();
389 erratum_a008336();
390 erratum_a009008();
391 erratum_a009798();
392 erratum_a008997();
393 erratum_a009007();
394 erratum_a050204();
395 #ifdef CONFIG_CHAIN_OF_TRUST
396 /* In case of Secure Boot, the IBR configures the SMMU
397 * to allow only Secure transactions.
398 * SMMU must be reset in bypass mode.
399 * Set the ClientPD bit and Clear the USFCFG Bit
400 */
401 if (fsl_check_boot_mode_secure() == 1)
402 bypass_smmu();
403 #endif
404
405 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
406 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
407 defined(CONFIG_ARCH_LX2162A)
408 set_icids();
409 #endif
410 }
411
412 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)413 int get_core_volt_from_fuse(void)
414 {
415 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
416 int vdd;
417 u32 fusesr;
418 u8 vid;
419
420 /* get the voltage ID from fuse status register */
421 fusesr = in_le32(&gur->dcfg_fusesr);
422 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
423 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
424 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
425 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
426 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
427 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
428 }
429 debug("%s: VID = 0x%x\n", __func__, vid);
430 switch (vid) {
431 case 0x00: /* VID isn't supported */
432 vdd = -EINVAL;
433 debug("%s: The VID feature is not supported\n", __func__);
434 break;
435 case 0x08: /* 0.9V silicon */
436 vdd = 900;
437 break;
438 case 0x10: /* 1.0V silicon */
439 vdd = 1000;
440 break;
441 default: /* Other core voltage */
442 vdd = -EINVAL;
443 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
444 break;
445 }
446 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
447
448 return vdd;
449 }
450
451 #elif defined(CONFIG_FSL_LSCH2)
452 /*
453 * This erratum requires setting a value to eddrtqcr1 to optimal
454 * the DDR performance. The eddrtqcr1 register is in SCFG space
455 * of LS1043A and the offset is 0x157_020c.
456 */
457 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
458 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
459 #error A009660 and A008514 can not be both enabled.
460 #endif
461
erratum_a009660(void)462 static void erratum_a009660(void)
463 {
464 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
465 u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
466 out_be32(eddrtqcr1, 0x63b20042);
467 #endif
468 }
469
erratum_a008850_early(void)470 static void erratum_a008850_early(void)
471 {
472 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
473 /* part 1 of 2 */
474 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
475 CONFIG_SYS_CCI400_OFFSET);
476 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
477
478 /* Skip if running at lower exception level */
479 if (current_el() < 3)
480 return;
481
482 /* disables propagation of barrier transactions to DDRC from CCI400 */
483 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
484
485 /* disable the re-ordering in DDRC */
486 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
487 #endif
488 }
489
erratum_a008850_post(void)490 void erratum_a008850_post(void)
491 {
492 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
493 /* part 2 of 2 */
494 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
495 CONFIG_SYS_CCI400_OFFSET);
496 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
497 u32 tmp;
498
499 /* Skip if running at lower exception level */
500 if (current_el() < 3)
501 return;
502
503 /* enable propagation of barrier transactions to DDRC from CCI400 */
504 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
505
506 /* enable the re-ordering in DDRC */
507 tmp = ddr_in32(&ddr->eor);
508 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
509 ddr_out32(&ddr->eor, tmp);
510 #endif
511 }
512
513 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315(void)514 void erratum_a010315(void)
515 {
516 int i;
517
518 for (i = PCIE1; i <= PCIE4; i++)
519 if (!is_serdes_configured(i)) {
520 debug("PCIe%d: disabled all R/W permission!\n", i);
521 set_pcie_ns_access(i, 0);
522 }
523 }
524 #endif
525
erratum_a010539(void)526 static void erratum_a010539(void)
527 {
528 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
529 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
530 u32 porsr1;
531
532 porsr1 = in_be32(&gur->porsr1);
533 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
534 out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
535 porsr1);
536 out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
537 #endif
538 }
539
540 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)541 int get_core_volt_from_fuse(void)
542 {
543 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
544 int vdd;
545 u32 fusesr;
546 u8 vid;
547
548 fusesr = in_be32(&gur->dcfg_fusesr);
549 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
550 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
551 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
552 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
553 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
554 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
555 }
556 debug("%s: VID = 0x%x\n", __func__, vid);
557 switch (vid) {
558 case 0x00: /* VID isn't supported */
559 vdd = -EINVAL;
560 debug("%s: The VID feature is not supported\n", __func__);
561 break;
562 case 0x08: /* 0.9V silicon */
563 vdd = 900;
564 break;
565 case 0x10: /* 1.0V silicon */
566 vdd = 1000;
567 break;
568 default: /* Other core voltage */
569 vdd = -EINVAL;
570 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
571 break;
572 }
573 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
574
575 return vdd;
576 }
577
board_switch_core_volt(u32 vdd)578 __weak int board_switch_core_volt(u32 vdd)
579 {
580 return 0;
581 }
582
setup_core_volt(u32 vdd)583 static int setup_core_volt(u32 vdd)
584 {
585 return board_setup_core_volt(vdd);
586 }
587
588 #ifdef CONFIG_SYS_FSL_DDR
ddr_enable_0v9_volt(bool en)589 static void ddr_enable_0v9_volt(bool en)
590 {
591 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
592 u32 tmp;
593
594 tmp = ddr_in32(&ddr->ddr_cdr1);
595
596 if (en)
597 tmp |= DDR_CDR1_V0PT9_EN;
598 else
599 tmp &= ~DDR_CDR1_V0PT9_EN;
600
601 ddr_out32(&ddr->ddr_cdr1, tmp);
602 }
603 #endif
604
setup_chip_volt(void)605 int setup_chip_volt(void)
606 {
607 int vdd;
608
609 vdd = get_core_volt_from_fuse();
610 /* Nothing to do for silicons doesn't support VID */
611 if (vdd < 0)
612 return vdd;
613
614 if (setup_core_volt(vdd))
615 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
616 #ifdef CONFIG_SYS_HAS_SERDES
617 if (setup_serdes_volt(vdd))
618 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
619 #endif
620
621 #ifdef CONFIG_SYS_FSL_DDR
622 if (vdd == 900)
623 ddr_enable_0v9_volt(true);
624 #endif
625
626 return 0;
627 }
628
629 #ifdef CONFIG_FSL_PFE
init_pfe_scfg_dcfg_regs(void)630 void init_pfe_scfg_dcfg_regs(void)
631 {
632 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
633 u32 ecccr2;
634
635 out_be32(&scfg->pfeasbcr,
636 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
637 out_be32(&scfg->pfebsbcr,
638 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
639
640 /* CCI-400 QoS settings for PFE */
641 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
642 | SCFG_WR_QOS1_PFE2_QOS));
643 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
644 | SCFG_RD_QOS1_PFE2_QOS));
645
646 ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
647 out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
648 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
649 }
650 #endif
651
fsl_lsch2_early_init_f(void)652 void fsl_lsch2_early_init_f(void)
653 {
654 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
655 CONFIG_SYS_CCI400_OFFSET);
656 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
657 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
658 enum boot_src src;
659 #endif
660
661 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
662 enable_layerscape_ns_access();
663 #endif
664
665 #ifdef CONFIG_FSL_IFC
666 init_early_memctl_regs(); /* tighten IFC timing */
667 #endif
668
669 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
670 src = get_boot_src();
671 if (src != BOOT_SOURCE_QSPI_NOR)
672 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
673 #else
674 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
675 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
676 #endif
677 #endif
678 /* Make SEC reads and writes snoopable */
679 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
680 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
681 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
682 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
683 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
684 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
685 SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
686 #elif defined(CONFIG_ARCH_LS1012A)
687 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
688 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
689 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
690 SCFG_SNPCNFGCR_SATAWRSNP);
691 #else
692 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
693 SCFG_SNPCNFGCR_SECWRSNP |
694 SCFG_SNPCNFGCR_SATARDSNP |
695 SCFG_SNPCNFGCR_SATAWRSNP);
696 #endif
697
698 /*
699 * Enable snoop requests and DVM message requests for
700 * Slave insterface S4 (A53 core cluster)
701 */
702 if (current_el() == 3) {
703 out_le32(&cci->slave[4].snoop_ctrl,
704 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
705 }
706
707 /*
708 * Program Central Security Unit (CSU) to grant access
709 * permission for USB 2.0 controller
710 */
711 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
712 if (current_el() == 3)
713 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
714 #endif
715 /* Erratum */
716 erratum_a008850_early(); /* part 1 of 2 */
717 erratum_a009660();
718 erratum_a010539();
719 erratum_a009008();
720 erratum_a009798();
721 erratum_a008997();
722 erratum_a009007();
723
724 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
725 set_icids();
726 #endif
727 }
728 #endif
729
730 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
fspi_ahb_init(void)731 int fspi_ahb_init(void)
732 {
733 /* Enable 4bytes address support and fast read */
734 u32 *fspi_lut, lut_key, *fspi_key;
735
736 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
737 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
738
739 lut_key = in_be32(fspi_key);
740
741 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
742 /* That means the register is BE */
743 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
744 /* Unlock the lut table */
745 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
746 /* Create READ LUT */
747 out_be32(fspi_lut, 0x0820040c);
748 out_be32(fspi_lut + 1, 0x24003008);
749 out_be32(fspi_lut + 2, 0x00000000);
750 /* Lock the lut table */
751 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
752 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
753 } else {
754 /* That means the register is LE */
755 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
756 /* Unlock the lut table */
757 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
758 /* Create READ LUT */
759 out_le32(fspi_lut, 0x0820040c);
760 out_le32(fspi_lut + 1, 0x24003008);
761 out_le32(fspi_lut + 2, 0x00000000);
762 /* Lock the lut table */
763 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
764 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
765 }
766
767 return 0;
768 }
769 #endif
770
771 #ifdef CONFIG_QSPI_AHB_INIT
772 /* Enable 4bytes address support and fast read */
qspi_ahb_init(void)773 int qspi_ahb_init(void)
774 {
775 u32 *qspi_lut, lut_key, *qspi_key;
776
777 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
778 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
779
780 lut_key = in_be32(qspi_key);
781
782 if (lut_key == 0x5af05af0) {
783 /* That means the register is BE */
784 out_be32(qspi_key, 0x5af05af0);
785 /* Unlock the lut table */
786 out_be32(qspi_key + 1, 0x00000002);
787 out_be32(qspi_lut, 0x0820040c);
788 out_be32(qspi_lut + 1, 0x1c080c08);
789 out_be32(qspi_lut + 2, 0x00002400);
790 /* Lock the lut table */
791 out_be32(qspi_key, 0x5af05af0);
792 out_be32(qspi_key + 1, 0x00000001);
793 } else {
794 /* That means the register is LE */
795 out_le32(qspi_key, 0x5af05af0);
796 /* Unlock the lut table */
797 out_le32(qspi_key + 1, 0x00000002);
798 out_le32(qspi_lut, 0x0820040c);
799 out_le32(qspi_lut + 1, 0x1c080c08);
800 out_le32(qspi_lut + 2, 0x00002400);
801 /* Lock the lut table */
802 out_le32(qspi_key, 0x5af05af0);
803 out_le32(qspi_key + 1, 0x00000001);
804 }
805
806 return 0;
807 }
808 #endif
809
810 #ifdef CONFIG_TFABOOT
811 #define MAX_BOOTCMD_SIZE 512
812
fsl_setenv_bootcmd(void)813 int fsl_setenv_bootcmd(void)
814 {
815 int ret;
816 enum boot_src src = get_boot_src();
817 char bootcmd_str[MAX_BOOTCMD_SIZE];
818
819 switch (src) {
820 #ifdef IFC_NOR_BOOTCOMMAND
821 case BOOT_SOURCE_IFC_NOR:
822 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
823 break;
824 #endif
825 #ifdef QSPI_NOR_BOOTCOMMAND
826 case BOOT_SOURCE_QSPI_NOR:
827 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
828 break;
829 #endif
830 #ifdef XSPI_NOR_BOOTCOMMAND
831 case BOOT_SOURCE_XSPI_NOR:
832 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
833 break;
834 #endif
835 #ifdef IFC_NAND_BOOTCOMMAND
836 case BOOT_SOURCE_IFC_NAND:
837 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
838 break;
839 #endif
840 #ifdef QSPI_NAND_BOOTCOMMAND
841 case BOOT_SOURCE_QSPI_NAND:
842 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
843 break;
844 #endif
845 #ifdef XSPI_NAND_BOOTCOMMAND
846 case BOOT_SOURCE_XSPI_NAND:
847 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
848 break;
849 #endif
850 #ifdef SD_BOOTCOMMAND
851 case BOOT_SOURCE_SD_MMC:
852 sprintf(bootcmd_str, SD_BOOTCOMMAND);
853 break;
854 #endif
855 #ifdef SD2_BOOTCOMMAND
856 case BOOT_SOURCE_SD_MMC2:
857 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
858 break;
859 #endif
860 default:
861 #ifdef QSPI_NOR_BOOTCOMMAND
862 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
863 #endif
864 break;
865 }
866
867 ret = env_set("bootcmd", bootcmd_str);
868 if (ret) {
869 printf("Failed to set bootcmd: ret = %d\n", ret);
870 return ret;
871 }
872 return 0;
873 }
874
fsl_setenv_mcinitcmd(void)875 int fsl_setenv_mcinitcmd(void)
876 {
877 int ret = 0;
878 enum boot_src src = get_boot_src();
879
880 switch (src) {
881 #ifdef IFC_MC_INIT_CMD
882 case BOOT_SOURCE_IFC_NAND:
883 case BOOT_SOURCE_IFC_NOR:
884 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
885 break;
886 #endif
887 #ifdef QSPI_MC_INIT_CMD
888 case BOOT_SOURCE_QSPI_NAND:
889 case BOOT_SOURCE_QSPI_NOR:
890 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
891 break;
892 #endif
893 #ifdef XSPI_MC_INIT_CMD
894 case BOOT_SOURCE_XSPI_NAND:
895 case BOOT_SOURCE_XSPI_NOR:
896 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
897 break;
898 #endif
899 #ifdef SD_MC_INIT_CMD
900 case BOOT_SOURCE_SD_MMC:
901 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
902 break;
903 #endif
904 #ifdef SD2_MC_INIT_CMD
905 case BOOT_SOURCE_SD_MMC2:
906 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
907 break;
908 #endif
909 default:
910 #ifdef QSPI_MC_INIT_CMD
911 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
912 #endif
913 break;
914 }
915
916 if (ret) {
917 printf("Failed to set mcinitcmd: ret = %d\n", ret);
918 return ret;
919 }
920 return 0;
921 }
922 #endif
923
924 #ifdef CONFIG_BOARD_LATE_INIT
fsl_board_late_init(void)925 __weak int fsl_board_late_init(void)
926 {
927 return 0;
928 }
929
930 #define DWC3_GSBUSCFG0 0xc100
931 #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
932 #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
933 << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
934
enable_dwc3_snooping(void)935 static void enable_dwc3_snooping(void)
936 {
937 static const char * const compatibles[] = {
938 "fsl,layerscape-dwc3",
939 "fsl,ls1028a-dwc3",
940 };
941 fdt_addr_t dwc3_base;
942 ofnode node;
943 u32 val;
944 int i;
945
946 for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
947 ofnode_for_each_compatible_node(node, compatibles[i]) {
948 dwc3_base = ofnode_get_addr(node);
949 if (dwc3_base == FDT_ADDR_T_NONE)
950 continue;
951
952 val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
953 val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
954 val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
955 writel(val, dwc3_base + DWC3_GSBUSCFG0);
956 }
957 }
958 }
959
board_late_init(void)960 int board_late_init(void)
961 {
962 #ifdef CONFIG_CHAIN_OF_TRUST
963 fsl_setenv_chain_of_trust();
964 #endif
965 #ifdef CONFIG_TFABOOT
966 /*
967 * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
968 * not exists in env
969 */
970 if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
971 // Set bootcmd and mcinitcmd as per boot source
972 fsl_setenv_bootcmd();
973 fsl_setenv_mcinitcmd();
974 env_set("fsl_bootcmd_mcinitcmd_set", "y");
975 }
976 #endif
977 #ifdef CONFIG_QSPI_AHB_INIT
978 qspi_ahb_init();
979 #endif
980 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
981 fspi_ahb_init();
982 #endif
983
984 if (IS_ENABLED(CONFIG_DM))
985 enable_dwc3_snooping();
986
987 return fsl_board_late_init();
988 }
989 #endif
990